Skip to content

Commit 2a1b5af

Browse files
jayfoadjayfoad
committed
[GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister
Summary: As a side effect some redundant copies of constant values are removed by CSEMIRBuilder. Reviewers: aemerson, arsenm, dsanders, aditya_nandakumar Subscribers: sdardis, jvesely, wdng, nhaehnle, rovka, hiraditya, jrtc27, atanasyan, volkan, Petar.Avramovic, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73789
1 parent 6c7efe2 commit 2a1b5af

17 files changed

+90
-157
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -847,8 +847,8 @@ class MachineIRBuilder {
847847
MachineInstrBuilder buildConcatVectors(const DstOp &Res,
848848
ArrayRef<Register> Ops);
849849

850-
MachineInstrBuilder buildInsert(Register Res, Register Src,
851-
Register Op, unsigned Index);
850+
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
851+
const SrcOp &Op, unsigned Index);
852852

853853
/// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
854854
/// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the

‎llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -650,22 +650,20 @@ MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
650650
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
651651
}
652652

653-
MachineInstrBuilder MachineIRBuilder::buildInsert(Register Res, Register Src,
654-
Register Op, unsigned Index) {
655-
assert(Index + getMRI()->getType(Op).getSizeInBits() <=
656-
getMRI()->getType(Res).getSizeInBits() &&
653+
MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
654+
const SrcOp &Src,
655+
const SrcOp &Op,
656+
unsigned Index) {
657+
assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
658+
Res.getLLTTy(*getMRI()).getSizeInBits() &&
657659
"insertion past the end of a register");
658660

659-
if (getMRI()->getType(Res).getSizeInBits() ==
660-
getMRI()->getType(Op).getSizeInBits()) {
661+
if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
662+
Op.getLLTTy(*getMRI()).getSizeInBits()) {
661663
return buildCast(Res, Op);
662664
}
663665

664-
return buildInstr(TargetOpcode::G_INSERT)
665-
.addDef(Res)
666-
.addUse(Src)
667-
.addUse(Op)
668-
.addImm(Index);
666+
return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
669667
}
670668

671669
MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,

‎llvm/lib/Target/AArch64/AArch64CallLowering.cpp

Lines changed: 8 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -62,10 +62,9 @@ struct IncomingArgHandler : public CallLowering::ValueHandler {
6262
auto &MFI = MIRBuilder.getMF().getFrameInfo();
6363
int FI = MFI.CreateFixedObject(Size, Offset, true);
6464
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
65-
Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
66-
MIRBuilder.buildFrameIndex(AddrReg, FI);
65+
auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
6766
StackUsed = std::max(StackUsed, Size + Offset);
68-
return AddrReg;
67+
return AddrReg.getReg(0);
6968
}
7069

7170
void assignValueToReg(Register ValVReg, Register PhysReg,
@@ -147,23 +146,19 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
147146
if (IsTailCall) {
148147
Offset += FPDiff;
149148
int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
150-
Register FIReg = MRI.createGenericVirtualRegister(p0);
151-
MIRBuilder.buildFrameIndex(FIReg, FI);
149+
auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
152150
MPO = MachinePointerInfo::getFixedStack(MF, FI);
153-
return FIReg;
151+
return FIReg.getReg(0);
154152
}
155153

156-
Register SPReg = MRI.createGenericVirtualRegister(p0);
157-
MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
154+
auto SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP));
158155

159-
Register OffsetReg = MRI.createGenericVirtualRegister(s64);
160-
MIRBuilder.buildConstant(OffsetReg, Offset);
156+
auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
161157

162-
Register AddrReg = MRI.createGenericVirtualRegister(p0);
163-
MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
158+
auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
164159

165160
MPO = MachinePointerInfo::getStack(MF, Offset);
166-
return AddrReg;
161+
return AddrReg.getReg(0);
167162
}
168163

169164
void assignValueToReg(Register ValVReg, Register PhysReg,

‎llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -709,12 +709,11 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
709709
const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize);
710710
auto &MMO = **MI.memoperands_begin();
711711
if (MI.getOpcode() == TargetOpcode::G_STORE) {
712-
auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg});
712+
auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg);
713713
MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO);
714714
} else {
715-
Register NewReg = MRI.createGenericVirtualRegister(NewTy);
716-
auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1), MMO);
717-
MIRBuilder.buildBitcast({ValReg}, {NewLoad});
715+
auto NewLoad = MIRBuilder.buildLoad(NewTy, MI.getOperand(1), MMO);
716+
MIRBuilder.buildBitcast(ValReg, NewLoad);
718717
}
719718
MI.eraseFromParent();
720719
return true;
@@ -733,21 +732,19 @@ bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
733732
LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
734733

735734
const unsigned PtrSize = PtrTy.getSizeInBits() / 8;
736-
Register List = MRI.createGenericVirtualRegister(PtrTy);
737-
MIRBuilder.buildLoad(
738-
List, ListPtr,
735+
auto List = MIRBuilder.buildLoad(
736+
PtrTy, ListPtr,
739737
*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
740738
PtrSize, /* Align = */ PtrSize));
741739

742-
Register DstPtr;
740+
MachineInstrBuilder DstPtr;
743741
if (Align > PtrSize) {
744742
// Realign the list to the actual required alignment.
745743
auto AlignMinus1 = MIRBuilder.buildConstant(IntPtrTy, Align - 1);
746744

747745
auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0));
748746

749-
DstPtr = MRI.createGenericVirtualRegister(PtrTy);
750-
MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align));
747+
DstPtr = MIRBuilder.buildPtrMask(PtrTy, ListTmp, Log2_64(Align));
751748
} else
752749
DstPtr = List;
753750

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 7 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -84,11 +84,10 @@ struct IncomingArgHandler : public CallLowering::ValueHandler {
8484
auto &MFI = MIRBuilder.getMF().getFrameInfo();
8585
int FI = MFI.CreateFixedObject(Size, Offset, true);
8686
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
87-
Register AddrReg = MRI.createGenericVirtualRegister(
88-
LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32));
89-
MIRBuilder.buildFrameIndex(AddrReg, FI);
87+
auto AddrReg = MIRBuilder.buildFrameIndex(
88+
LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32), FI);
9089
StackUsed = std::max(StackUsed, Size + Offset);
91-
return AddrReg;
90+
return AddrReg.getReg(0);
9291
}
9392

9493
void assignValueToReg(Register ValVReg, Register PhysReg,
@@ -222,9 +221,6 @@ static void unpackRegsToOrigType(MachineIRBuilder &B,
222221
LLT PartTy) {
223222
assert(DstRegs.size() > 1 && "Nothing to unpack");
224223

225-
MachineFunction &MF = B.getMF();
226-
MachineRegisterInfo &MRI = MF.getRegInfo();
227-
228224
const unsigned SrcSize = SrcTy.getSizeInBits();
229225
const unsigned PartSize = PartTy.getSizeInBits();
230226

@@ -248,12 +244,11 @@ static void unpackRegsToOrigType(MachineIRBuilder &B,
248244
LLT BigTy = getMultipleType(PartTy, NumRoundedParts);
249245
auto ImpDef = B.buildUndef(BigTy);
250246

251-
Register BigReg = MRI.createGenericVirtualRegister(BigTy);
252-
B.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
247+
auto Big = B.buildInsert(BigTy, ImpDef.getReg(0), SrcReg, 0).getReg(0);
253248

254249
int64_t Offset = 0;
255250
for (unsigned i = 0, e = DstRegs.size(); i != e; ++i, Offset += PartSize)
256-
B.buildExtract(DstRegs[i], BigReg, Offset);
251+
B.buildExtract(DstRegs[i], Big, Offset);
257252
}
258253

259254
/// Lower the return value for the already existing \p Ret. This assumes that
@@ -348,17 +343,13 @@ Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &B,
348343
const DataLayout &DL = F.getParent()->getDataLayout();
349344
PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUAS::CONSTANT_ADDRESS);
350345
LLT PtrType = getLLTForType(*PtrTy, DL);
351-
Register DstReg = MRI.createGenericVirtualRegister(PtrType);
352346
Register KernArgSegmentPtr =
353347
MFI->getPreloadedReg(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
354348
Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
355349

356-
Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
357-
B.buildConstant(OffsetReg, Offset);
358-
359-
B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
350+
auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset);
360351

361-
return DstReg;
352+
return B.buildPtrAdd(PtrType, KernArgSegmentVReg, OffsetReg).getReg(0);
362353
}
363354

364355
void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 11 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1226,7 +1226,6 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
12261226
Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
12271227
WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
12281228

1229-
Register ApertureReg = MRI.createGenericVirtualRegister(S32);
12301229
Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
12311230

12321231
B.buildInstr(AMDGPU::S_GETREG_B32)
@@ -1235,9 +1234,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
12351234
MRI.setType(GetReg, S32);
12361235

12371236
auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1);
1238-
B.buildShl(ApertureReg, GetReg, ShiftAmt);
1239-
1240-
return ApertureReg;
1237+
return B.buildShl(S32, GetReg, ShiftAmt).getReg(0);
12411238
}
12421239

12431240
Register QueuePtr = MRI.createGenericVirtualRegister(
@@ -1261,12 +1258,10 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
12611258
4,
12621259
MinAlign(64, StructOffset));
12631260

1264-
Register LoadResult = MRI.createGenericVirtualRegister(S32);
12651261
Register LoadAddr;
12661262

12671263
B.materializePtrAdd(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
1268-
B.buildLoad(LoadResult, LoadAddr, *MMO);
1269-
return LoadResult;
1264+
return B.buildLoad(S32, LoadAddr, *MMO).getReg(0);
12701265
}
12711266

12721267
bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
@@ -1327,13 +1322,11 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
13271322
auto SegmentNull = B.buildConstant(DstTy, NullVal);
13281323
auto FlatNull = B.buildConstant(SrcTy, 0);
13291324

1330-
Register PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
1331-
13321325
// Extract low 32-bits of the pointer.
1333-
B.buildExtract(PtrLo32, Src, 0);
1326+
auto PtrLo32 = B.buildExtract(DstTy, Src, 0);
13341327

1335-
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
1336-
B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
1328+
auto CmpRes =
1329+
B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src, FlatNull.getReg(0));
13371330
B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
13381331

13391332
MI.eraseFromParent();
@@ -1355,19 +1348,16 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
13551348
if (!ApertureReg.isValid())
13561349
return false;
13571350

1358-
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
1359-
B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
1360-
1361-
Register BuildPtr = MRI.createGenericVirtualRegister(DstTy);
1351+
auto CmpRes =
1352+
B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src, SegmentNull.getReg(0));
13621353

13631354
// Coerce the type of the low half of the result so we can use merge_values.
1364-
Register SrcAsInt = MRI.createGenericVirtualRegister(S32);
1365-
B.buildPtrToInt(SrcAsInt, Src);
1355+
Register SrcAsInt = B.buildPtrToInt(S32, Src).getReg(0);
13661356

13671357
// TODO: Should we allow mismatched types but matching sizes in merges to
13681358
// avoid the ptrtoint?
1369-
B.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
1370-
B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
1359+
auto BuildPtr = B.buildMerge(DstTy, {SrcAsInt, ApertureReg});
1360+
B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull);
13711361

13721362
MI.eraseFromParent();
13731363
return true;
@@ -2281,8 +2271,6 @@ bool AMDGPULegalizerInfo::legalizeFDIV64(MachineInstr &MI,
22812271
// Workaround a hardware bug on SI where the condition output from div_scale
22822272
// is not usable.
22832273

2284-
Scale = MRI.createGenericVirtualRegister(S1);
2285-
22862274
LLT S32 = LLT::scalar(32);
22872275

22882276
auto NumUnmerge = B.buildUnmerge(S32, LHS);
@@ -2294,7 +2282,7 @@ bool AMDGPULegalizerInfo::legalizeFDIV64(MachineInstr &MI,
22942282
Scale1Unmerge.getReg(1));
22952283
auto CmpDen = B.buildICmp(ICmpInst::ICMP_EQ, S1, DenUnmerge.getReg(1),
22962284
Scale0Unmerge.getReg(1));
2297-
B.buildXor(Scale, CmpNum, CmpDen);
2285+
Scale = B.buildXor(S1, CmpNum, CmpDen).getReg(0);
22982286
} else {
22992287
Scale = DivScale1.getReg(1);
23002288
}

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1180,8 +1180,7 @@ bool AMDGPURegisterBankInfo::applyMappingWideLoad(MachineInstr &MI,
11801180
B.setInsertPt(*RepairInst->getParent(), RepairInst);
11811181

11821182
for (unsigned DefIdx = 0, e = DefRegs.size(); DefIdx != e; ++DefIdx) {
1183-
Register IdxReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
1184-
B.buildConstant(IdxReg, DefIdx);
1183+
Register IdxReg = B.buildConstant(LLT::scalar(32), DefIdx).getReg(0);
11851184
MRI.setRegBank(IdxReg, AMDGPU::VGPRRegBank);
11861185
B.buildExtractVectorElement(DefRegs[DefIdx], TmpReg, IdxReg);
11871186
}

‎llvm/lib/Target/ARM/ARMCallLowering.cpp

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -99,17 +99,14 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
9999

100100
LLT p0 = LLT::pointer(0, 32);
101101
LLT s32 = LLT::scalar(32);
102-
Register SPReg = MRI.createGenericVirtualRegister(p0);
103-
MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
102+
auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
104103

105-
Register OffsetReg = MRI.createGenericVirtualRegister(s32);
106-
MIRBuilder.buildConstant(OffsetReg, Offset);
104+
auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
107105

108-
Register AddrReg = MRI.createGenericVirtualRegister(p0);
109-
MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
106+
auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
110107

111108
MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
112-
return AddrReg;
109+
return AddrReg.getReg(0);
113110
}
114111

115112
void assignValueToReg(Register ValVReg, Register PhysReg,
@@ -299,11 +296,8 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {
299296
int FI = MFI.CreateFixedObject(Size, Offset, true);
300297
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
301298

302-
Register AddrReg =
303-
MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
304-
MIRBuilder.buildFrameIndex(AddrReg, FI);
305-
306-
return AddrReg;
299+
return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI)
300+
.getReg(0);
307301
}
308302

309303
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
@@ -318,20 +312,20 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {
318312
Size = 4;
319313
assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
320314

321-
auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
322-
buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
315+
auto LoadVReg =
316+
buildLoad(LLT::scalar(32), Addr, Size, /* Alignment */ 1, MPO);
323317
MIRBuilder.buildTrunc(ValVReg, LoadVReg);
324318
} else {
325319
// If the value is not extended, a simple load will suffice.
326320
buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
327321
}
328322
}
329323

330-
void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
331-
MachinePointerInfo &MPO) {
324+
MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
325+
unsigned Alignment, MachinePointerInfo &MPO) {
332326
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
333327
MPO, MachineMemOperand::MOLoad, Size, Alignment);
334-
MIRBuilder.buildLoad(Val, Addr, *MMO);
328+
return MIRBuilder.buildLoad(Res, Addr, *MMO);
335329
}
336330

337331
void assignValueToReg(Register ValVReg, Register PhysReg,
@@ -354,9 +348,7 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {
354348
// We cannot create a truncating copy, nor a trunc of a physical register.
355349
// Therefore, we need to copy the content of the physical register into a
356350
// virtual one and then truncate that.
357-
auto PhysRegToVReg =
358-
MRI.createGenericVirtualRegister(LLT::scalar(LocSize));
359-
MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
351+
auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
360352
MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
361353
}
362354
}

‎llvm/lib/Target/ARM/ARMLegalizerInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -445,8 +445,7 @@ bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
445445
} else {
446446
// We need to compare against 0.
447447
assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
448-
auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
449-
MIRBuilder.buildConstant(Zero, 0);
448+
auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0);
450449
MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
451450
}
452451
Results.push_back(ProcessedResult);

0 commit comments

Comments
 (0)