Skip to content

Commit 2e902a8

Browse files
michael-roememfrob
michael-roe
authored and
memfrob
committed
[mips] Implement add.ps, mul.ps and sub.ps
Differential revision: https://reviews.llvm.org/D90321
1 parent 2c5394f commit 2e902a8

20 files changed

+39
-29
lines changed

‎llvm/lib/Target/Mips/MipsInstrFPU.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -452,6 +452,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
452452

453453
let DecoderNamespace = "MipsFP64" in {
454454
let AdditionalPredicates = [NotInMicroMips] in {
455+
def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, II_ADD_PS, 0>,
456+
ADDS_FM<0x0, 22>,
457+
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
458+
def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, II_MUL_PS, 0>,
459+
ADDS_FM<0x2, 22>,
460+
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
455461
def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
456462
ADDS_FM<0x2C, 22>,
457463
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
@@ -464,6 +470,9 @@ let DecoderNamespace = "MipsFP64" in {
464470
def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
465471
ADDS_FM<0x2F, 22>,
466472
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
473+
def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, II_SUB_PS, 0>,
474+
ADDS_FM<0x1, 22>,
475+
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
467476

468477
def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
469478
ABSS_FM<0x20, 22>,

‎llvm/lib/Target/Mips/MipsSchedule.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ def II_ADDIUPC : InstrItinClass;
2626
def II_ADD : InstrItinClass;
2727
def II_ADDU : InstrItinClass;
2828
def II_ADD_D : InstrItinClass;
29+
def II_ADD_PS : InstrItinClass;
2930
def II_ADD_S : InstrItinClass;
3031
def II_ADDR_PS : InstrItinClass;
3132
def II_ALIGN : InstrItinClass;
@@ -279,6 +280,7 @@ def II_MUL : InstrItinClass;
279280
def II_MUH : InstrItinClass;
280281
def II_MUHU : InstrItinClass;
281282
def II_MULU : InstrItinClass;
283+
def II_MUL_PS : InstrItinClass;
282284
def II_MULR_PS : InstrItinClass;
283285
def II_MULT : InstrItinClass;
284286
def II_MULTU : InstrItinClass;
@@ -341,6 +343,7 @@ def II_SRLV : InstrItinClass;
341343
def II_SUB : InstrItinClass;
342344
def II_SUBU : InstrItinClass;
343345
def II_SUB_D : InstrItinClass;
346+
def II_SUB_PS : InstrItinClass;
344347
def II_SUB_S : InstrItinClass;
345348
def II_SUXC1 : InstrItinClass;
346349
def II_SW : InstrItinClass;

‎llvm/lib/Target/Mips/MipsScheduleGeneric.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -829,10 +829,11 @@ def : InstRW<[GenericWriteFPUL], (instrs ADDR_PS64,
829829
CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L,
830830
CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S,
831831
CVT_PS_S64, CVT_S_PL64, CVT_S_PU64,
832-
CVT_PS_PW64, CVT_PW_PS64,
832+
CVT_PS_PW64, CVT_PW_PS64, FADD_PS64,
833833
FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32,
834834
FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,
835-
MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, MULR_PS64,
835+
FMUL_PS64, FSUB_PS64, MADD_D32, MADD_D64,
836+
MSUB_D32, MSUB_D64, MULR_PS64,
836837
NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,
837838
PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64,
838839
ROUND_L_D64, ROUND_L_S, ROUND_W_D32,

‎llvm/lib/Target/Mips/MipsScheduleP5600.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -449,8 +449,8 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>;
449449
// cvt.ps.[sw], cvt.s.(pl|pu), c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps,
450450
// pl[lu].ps, sub.[ds], sub.ps, trunc.w.[ds], trunc.w.ps
451451
def : InstRW<[P5600WriteFPUL],
452-
(instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
453-
FSUB_D32, FSUB_D64, FSUB_S)>;
452+
(instrs FADD_D32, FADD_D64, FADD_PS64, FADD_S, FMUL_D32, FMUL_D64,
453+
FMUL_PS64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_PS64, FSUB_S)>;
454454
def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>;
455455
def : InstRW<[P5600WriteFPUL],
456456
(instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>;

‎llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77

88
.set noat
99
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10-
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1110
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1211
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1312
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
@@ -32,11 +31,9 @@
3231
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3332
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3433
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35-
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3634
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3735
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3836
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39-
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
4037
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
4138
c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
4239
c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level

‎llvm/test/MC/Mips/mips1/invalid-mips5.s

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
# RUN: FileCheck %s < %t1
66

77
.set noat
8+
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
89
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
910
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
1011
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@@ -71,6 +72,7 @@
7172
movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7273
movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7374
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
75+
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7476
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7577
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7678
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@@ -81,6 +83,7 @@
8183
round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8284
sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8385
sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
86+
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8487
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8588
teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8689
tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

‎llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77

88
.set noat
99
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10-
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1110
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1211
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1312
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
@@ -32,8 +31,6 @@
3231
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3332
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3433
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35-
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3634
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3735
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3836
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39-
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

‎llvm/test/MC/Mips/mips2/invalid-mips5.s

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
# RUN: FileCheck %s < %t1
66

77
.set noat
8+
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
89
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
910
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
1011
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@@ -67,6 +68,7 @@
6768
movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6869
movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6970
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
71+
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7072
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7173
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7274
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@@ -76,6 +78,7 @@
7678
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7779
trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7880
sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
81+
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7982
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8083
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8184
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level

‎llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77

88
.set noat
99
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10-
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1110
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1211
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
1312
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
@@ -32,9 +31,6 @@
3231
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3332
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3433
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35-
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3634
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3735
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3836
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39-
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
40-

‎llvm/test/MC/Mips/mips3/invalid-mips5.s

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
# RUN: FileCheck %s < %t1
66

77
.set noat
8+
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
89
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
910
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
1011
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@@ -30,11 +31,13 @@
3031
movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3132
movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3233
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34+
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3335
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3436
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3537
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3638
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3739
sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40+
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3841
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3942
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
4043
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level

0 commit comments

Comments
 (0)