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AMDGPU/GlobalISel: Make use of MachineIRBuilder helper functions. NFC.
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llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1235,10 +1235,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
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MRI.setType(GetReg, S32);
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auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1);
1238-
B.buildInstr(TargetOpcode::G_SHL)
1239-
.addDef(ApertureReg)
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.addUse(GetReg)
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.addUse(ShiftAmt.getReg(0));
1238+
B.buildShl(ApertureReg, GetReg, ShiftAmt);
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return ApertureReg;
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}
@@ -1365,9 +1362,7 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
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// Coerce the type of the low half of the result so we can use merge_values.
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Register SrcAsInt = MRI.createGenericVirtualRegister(S32);
1368-
B.buildInstr(TargetOpcode::G_PTRTOINT)
1369-
.addDef(SrcAsInt)
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.addUse(Src);
1365+
B.buildPtrToInt(SrcAsInt, Src);
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// TODO: Should we allow mismatched types but matching sizes in merges to
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// avoid the ptrtoint?
@@ -1420,7 +1415,7 @@ bool AMDGPULegalizerInfo::legalizeFceil(
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// if (src > 0.0 && src != result)
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// result += 1.0
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1423-
auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src});
1418+
auto Trunc = B.buildIntrinsicTrunc(S64, Src);
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const auto Zero = B.buildFConstant(S64, 0.0);
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const auto One = B.buildFConstant(S64, 1.0);

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