Revert "[RISCV] Add IR intrinsic for Zbb extension"

This reverts commit 1808194590dd2b308bc146406425d5d52e46b7e6.

I forgot to change the author.

Author: topperc

clang/include/clang/Basic/BuiltinsRISCV.def

@@ -17,10 +17,6 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
-// Zbb extension
-TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
-TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb")
-
 // Zbr extension
 TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")

clang/include/clang/Basic/DiagnosticSemaKinds.td

@@ -11187,5 +11187,5 @@ def warn_tcb_enforcement_violation : Warning<
 
 // RISC-V builtin required extension warning
 def err_riscv_builtin_requires_extension : Error<
-  "builtin requires '%0' extension support to be enabled">;
+  "builtin requires %0 extension support to be enabled">;
 } // end of sema component.

clang/lib/CodeGen/CGBuiltin.cpp

@@ -17877,13 +17877,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   switch (BuiltinID) {
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
 
-  // Zbb
-  case RISCV::BI__builtin_riscv_orc_b_32:
-  case RISCV::BI__builtin_riscv_orc_b_64:
-    ID = Intrinsic::riscv_orc_b;
-    IntrinsicTypes = {ResultType};
-    break;
-
   // Zbr
   case RISCV::BI__builtin_riscv_crc32_b:
     ID = Intrinsic::riscv_crc32_b;
@@ -17917,8 +17910,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
     ID = Intrinsic::riscv_crc32c_d;
     IntrinsicTypes = {ResultType};
     break;
-  default:
+  default: {
     llvm_unreachable("unexpected builtin ID");
+    return nullptr;
+  } // default
   }
 
   assert(ID != Intrinsic::not_intrinsic);

clang/lib/Sema/SemaChecking.cpp

@@ -3424,7 +3424,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
   for (auto &I : ReqFeatures) {
     if (TI.hasFeature(I))
       continue;
-    // Convert features like "zbr" and "experimental-zbr" to "Zbr".
+    // Make message like "experimental-zbr" to "Zbr"
     I.consume_front("experimental-");
     std::string FeatureStr = I.str();
     FeatureStr[0] = std::toupper(FeatureStr[0]);

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

@@ -10,6 +10,28 @@
 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbr extension part
+
+let TargetPrefix = "riscv" in {
+
+    class BitMan_GPR_Intrinsics
+        : Intrinsic<[llvm_any_ty],
+                    [LLVMMatchType<0>],
+                    [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+
+    def int_riscv_crc32_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_d : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_d : BitMan_GPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
 //===----------------------------------------------------------------------===//
 // Atomics
 
@@ -67,30 +89,6 @@ let TargetPrefix = "riscv" in {
 
 } // TargetPrefix = "riscv"
 
-//===----------------------------------------------------------------------===//
-// Bitmanip (Bit Manipulation) Extension
-
-let TargetPrefix = "riscv" in {
-
-  class BitManipGPRIntrinsics
-      : Intrinsic<[llvm_any_ty],
-                  [LLVMMatchType<0>],
-                  [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-
-  // Zbb
-  def int_riscv_orc_b : BitManipGPRIntrinsics;
-
-  // Zbr
-  def int_riscv_crc32_b : BitManipGPRIntrinsics;
-  def int_riscv_crc32_h : BitManipGPRIntrinsics;
-  def int_riscv_crc32_w : BitManipGPRIntrinsics;
-  def int_riscv_crc32_d : BitManipGPRIntrinsics;
-  def int_riscv_crc32c_b : BitManipGPRIntrinsics;
-  def int_riscv_crc32c_h : BitManipGPRIntrinsics;
-  def int_riscv_crc32c_w : BitManipGPRIntrinsics;
-  def int_riscv_crc32c_d : BitManipGPRIntrinsics;
-} // TargetPrefix = "riscv"
-
 //===----------------------------------------------------------------------===//
 // Vectors
 

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

@@ -198,9 +198,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
-  if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
-    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
-
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::ADD, MVT::i32, Custom);
     setOperationAction(ISD::SUB, MVT::i32, Custom);
@@ -4201,14 +4198,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
     default:
       llvm_unreachable(
           "Don't know how to custom type legalize this intrinsic!");
-    case Intrinsic::riscv_orc_b: {
-      SDValue Newop1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue Res = 
-          DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), Newop1);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      return;
-    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -894,10 +894,6 @@ def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
-let Predicates = [HasStdExtZbb] in {
-def : PatGpr<int_riscv_orc_b, ORCB>;
-} // Predicates = [HasStdExtZbb]
-
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr<int_riscv_crc32_b, CRC32B>;
 def : PatGpr<int_riscv_crc32_h, CRC32H>;