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arsenmarsenm
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AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
1 parent a10527c commit 555e7ee

39 files changed

+194
-197
lines changed

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1784,7 +1784,7 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
17841784
&AMDGPU::SReg_32RegClass;
17851785
case 64:
17861786
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :
1787-
&AMDGPU::SReg_64_XEXECRegClass;
1787+
&AMDGPU::SReg_64RegClass;
17881788
case 96:
17891789
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass :
17901790
&AMDGPU::SReg_96RegClass;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,14 +97,14 @@ body: |
9797
liveins: $sgpr0_sgpr1, $vgpr0
9898
; WAVE64-LABEL: name: class_s64_vcc_sv
9999
; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
100-
; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
100+
; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
101101
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
102102
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
103103
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
104104
; WAVE32-LABEL: name: class_s64_vcc_sv
105105
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
106106
; WAVE32: $vcc_hi = IMPLICIT_DEF
107-
; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
107+
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
108108
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
109109
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
110110
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ body: |
5454
5555
; CHECK-LABEL: name: fract_s64_vs
5656
; CHECK: liveins: $sgpr0_sgpr1
57-
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
57+
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
5858
; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $exec
5959
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]
6060
%0:sgpr(s64) = COPY $sgpr0_sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ body: |
7575
liveins: $sgpr0_sgpr1, $vgpr0
7676
; GCN-LABEL: name: ldexp_s64_vsv
7777
; GCN: liveins: $sgpr0_sgpr1, $vgpr0
78-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
78+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
7979
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
8080
; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
8181
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ body: |
5454
5555
; CHECK-LABEL: name: rcp_s64_vs
5656
; CHECK: liveins: $sgpr0_sgpr1
57-
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
57+
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
5858
; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $exec
5959
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]
6060
%0:sgpr(s64) = COPY $sgpr0_sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ body: |
5454
5555
; CHECK-LABEL: name: rsq_s64_vs
5656
; CHECK: liveins: $sgpr0_sgpr1
57-
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
57+
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
5858
; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $exec
5959
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]
6060
%0:sgpr(s64) = COPY $sgpr0_sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ body: |
5151
5252
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
5353
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
54-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
54+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[COPY]]
5555
; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
5656
%0:sgpr(s32) = COPY $sgpr0
5757
%1:sgpr(s16) = G_TRUNC %0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -214,28 +214,28 @@ body: |
214214
bb.0:
215215
liveins: $sgpr0_sgpr1, $vgpr0
216216
; GFX6-LABEL: name: ashr_s64_sv
217-
; GFX6: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
217+
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
218218
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
219219
; GFX6: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec
220220
; GFX6: S_ENDPGM 0, implicit [[V_ASHR_I64_]]
221221
; GFX7-LABEL: name: ashr_s64_sv
222-
; GFX7: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
222+
; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
223223
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
224224
; GFX7: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec
225225
; GFX7: S_ENDPGM 0, implicit [[V_ASHR_I64_]]
226226
; GFX8-LABEL: name: ashr_s64_sv
227-
; GFX8: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
227+
; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
228228
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
229229
; GFX8: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
230230
; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
231231
; GFX9-LABEL: name: ashr_s64_sv
232-
; GFX9: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
232+
; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
233233
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
234234
; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
235235
; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
236236
; GFX10-LABEL: name: ashr_s64_sv
237237
; GFX10: $vcc_hi = IMPLICIT_DEF
238-
; GFX10: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
238+
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
239239
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
240240
; GFX10: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec
241241
; GFX10: S_ENDPGM 0, implicit [[V_ASHR_I64_]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ body: |
8181
; GCN: liveins: $sgpr0, $sgpr1
8282
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
8383
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
84-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
84+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
8585
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
8686
%0:sgpr(s32) = COPY $sgpr0
8787
%1:sgpr(s32) = COPY $sgpr1
@@ -102,7 +102,7 @@ body: |
102102
; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32
103103
; GCN: liveins: $sgpr0
104104
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
105-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1
105+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1
106106
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
107107
%1:sgpr(s32) = COPY $sgpr0
108108
%2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1
@@ -122,7 +122,7 @@ body: |
122122
; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32
123123
; GCN: liveins: $sgpr0
124124
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
125-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1
125+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1
126126
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
127127
%0:sgpr(s32) = COPY $sgpr0
128128
%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32),
@@ -141,8 +141,8 @@ body: |
141141
142142
; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64
143143
; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
144-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
145-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
144+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
145+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
146146
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
147147
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
148148
%0:sgpr(s64) = COPY $sgpr0_sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ body: |
8080
; GCN-LABEL: name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16
8181
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
8282
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
83-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
83+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
8484
; GCN: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
8585
%0:sgpr(<2 x s16>) = COPY $sgpr0
8686
%1:sgpr(<2 x s16>) = COPY $sgpr1
@@ -190,8 +190,8 @@ body: |
190190
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
191191
192192
; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v4s16_s_v4s16
193-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
194-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
193+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
194+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
195195
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
196196
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
197197
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
@@ -326,10 +326,10 @@ body: |
326326
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
327327
328328
; GCN-LABEL: name: test_concat_vectors_s_v16s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16
329-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
330-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
331-
; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
332-
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
329+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
330+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
331+
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
332+
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
333333
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7
334334
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
335335
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
@@ -390,14 +390,14 @@ body: |
390390
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15
391391
392392
; GCN-LABEL: name: test_concat_vectors_s_v32s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16
393-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
394-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
395-
; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
396-
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
397-
; GCN: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr8_sgpr9
398-
; GCN: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
399-
; GCN: [[COPY6:%[0-9]+]]:sreg_64_xexec = COPY $sgpr12_sgpr13
400-
; GCN: [[COPY7:%[0-9]+]]:sreg_64_xexec = COPY $sgpr14_sgpr15
393+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
394+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
395+
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
396+
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
397+
; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
398+
; GCN: [[COPY5:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
399+
; GCN: [[COPY6:%[0-9]+]]:sreg_64 = COPY $sgpr12_sgpr13
400+
; GCN: [[COPY7:%[0-9]+]]:sreg_64 = COPY $sgpr14_sgpr15
401401
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7, [[COPY4]], %subreg.sub8_sub9, [[COPY5]], %subreg.sub10_sub11, [[COPY6]], %subreg.sub12_sub13, [[COPY7]], %subreg.sub14_sub15
402402
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
403403
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
@@ -459,8 +459,8 @@ body: |
459459
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
460460
461461
; GCN-LABEL: name: test_concat_vectors_s_v4s32_s_v2s32_s_v2s32
462-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
463-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
462+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
463+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
464464
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
465465
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
466466
%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
@@ -499,10 +499,10 @@ body: |
499499
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
500500
501501
; GCN-LABEL: name: test_concat_vectors_s_v8s32_s_v2s32_s_v2s32_s_v2s32_s_v2s32
502-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
503-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
504-
; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
505-
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
502+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
503+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
504+
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
505+
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
506506
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7
507507
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
508508
%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
@@ -700,8 +700,8 @@ body: |
700700
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
701701
702702
; GCN-LABEL: name: test_concat_vectors_s_v4p3_s_v2p3_s_v2p3
703-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
704-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
703+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
704+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
705705
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
706706
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
707707
%0:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1
@@ -720,10 +720,10 @@ body: |
720720
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
721721
722722
; GCN-LABEL: name: test_concat_vectors_s_v8p3_s_v2p3_s_v2p3_v2p3_s_v2p3
723-
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
724-
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
725-
; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
726-
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
723+
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
724+
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
725+
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
726+
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
727727
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7
728728
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
729729
%0:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1

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