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Reapply "[M68k][GloballSel] Formal arguments lowering in IRTranslator"
Implementation of formal arguments lowering in the IRTranslator for the M68k backend Differential Revision: https://reviews.llvm.org/D104542
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5 files changed

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-4
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‎llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

Lines changed: 61 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,17 @@
1515
#include "M68kCallLowering.h"
1616
#include "M68kISelLowering.h"
1717
#include "M68kInstrInfo.h"
18+
#include "M68kSubtarget.h"
19+
#include "M68kTargetMachine.h"
20+
#include "llvm/CodeGen/CallingConvLower.h"
21+
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
1822
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
23+
#include "llvm/CodeGen/TargetCallingConv.h"
24+
1925
using namespace llvm;
2026

2127
M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
2228
: CallLowering(&TLI) {}
23-
2429
bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
2530
const Value *Val, ArrayRef<Register> VRegs,
2631
FunctionLoweringInfo &FLI,
@@ -36,11 +41,63 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
3641
const Function &F,
3742
ArrayRef<ArrayRef<Register>> VRegs,
3843
FunctionLoweringInfo &FLI) const {
44+
MachineFunction &MF = MIRBuilder.getMF();
45+
MachineRegisterInfo &MRI = MF.getRegInfo();
46+
const auto &DL = F.getParent()->getDataLayout();
47+
auto &TLI = *getTLI<M68kTargetLowering>();
3948

40-
if (F.arg_empty())
41-
return true;
49+
SmallVector<ArgInfo, 8> SplitArgs;
50+
unsigned I = 0;
51+
for (const auto &Arg : F.args()) {
52+
ArgInfo OrigArg{VRegs[I], Arg.getType()};
53+
setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
54+
splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
55+
++I;
56+
}
4257

43-
return false;
58+
CCAssignFn *AssignFn =
59+
TLI.getCCAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
60+
IncomingValueAssigner ArgAssigner(AssignFn);
61+
FormalArgHandler ArgHandler(MIRBuilder, MRI);
62+
return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
63+
MIRBuilder, F.getCallingConv(),
64+
F.isVarArg());
65+
}
66+
67+
void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
68+
Register PhysReg,
69+
CCValAssign &VA) {
70+
MIRBuilder.getMRI()->addLiveIn(PhysReg);
71+
MIRBuilder.getMBB().addLiveIn(PhysReg);
72+
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
73+
}
74+
75+
void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
76+
Register Addr,
77+
uint64_t Size,
78+
MachinePointerInfo &MPO,
79+
CCValAssign &VA) {
80+
MachineFunction &MF = MIRBuilder.getMF();
81+
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
82+
inferAlignFromPtrInfo(MF, MPO));
83+
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
84+
}
85+
86+
Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
87+
int64_t Offset,
88+
MachinePointerInfo &MPO,
89+
ISD::ArgFlagsTy Flags) {
90+
auto &MFI = MIRBuilder.getMF().getFrameInfo();
91+
const bool IsImmutable = !Flags.isByVal();
92+
int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
93+
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
94+
95+
// Build Frame Index
96+
llvm::LLT FramePtr = LLT::pointer(
97+
0, MIRBuilder.getMF().getDataLayout().getPointerSizeInBits());
98+
MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI);
99+
StackUsed = std::max(StackUsed, Size + Offset);
100+
return AddrReg.getReg(0);
44101
}
45102

46103
bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,

‎llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,29 @@ class M68kCallLowering : public CallLowering {
4343

4444
bool enableBigEndian() const override;
4545
};
46+
struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
47+
M68kIncomingValueHandler(MachineIRBuilder &MIRBuilder,
48+
MachineRegisterInfo &MRI)
49+
: CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}
50+
51+
uint64_t StackUsed;
52+
53+
private:
54+
void assignValueToReg(Register ValVReg, Register PhysReg,
55+
CCValAssign &VA) override;
56+
57+
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
58+
MachinePointerInfo &MPO, CCValAssign &VA) override;
59+
60+
Register getStackAddress(uint64_t Size, int64_t Offset,
61+
MachinePointerInfo &MPO,
62+
ISD::ArgFlagsTy Flags) override;
63+
};
64+
65+
struct FormalArgHandler : public M68kIncomingValueHandler {
66+
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
67+
: M68kIncomingValueHandler(MIRBuilder, MRI) {}
68+
};
4669

4770
} // end namespace llvm
4871

‎llvm/lib/Target/M68k/M68kISelLowering.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3412,3 +3412,9 @@ const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
34123412
return NULL;
34133413
}
34143414
}
3415+
3416+
CCAssignFn *M68kTargetLowering::getCCAssignFnForCall(CallingConv::ID CC,
3417+
bool Return,
3418+
bool IsVarArg) const {
3419+
return CC_M68k_C;
3420+
}

‎llvm/lib/Target/M68k/M68kISelLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,9 @@ class M68kTargetLowering : public TargetLowering {
171171
EmitInstrWithCustomInserter(MachineInstr &MI,
172172
MachineBasicBlock *MBB) const override;
173173

174+
CCAssignFn *getCCAssignFnForCall(CallingConv::ID CC, bool Return,
175+
bool IsVarArg) const;
176+
174177
private:
175178
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
176179
SelectionDAG &DAG) const;

‎llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

Lines changed: 170 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,177 @@
11
; RUN: llc -mtriple=m68k -global-isel -stop-after=irtranslator < %s | FileCheck %s
22

3+
34
; CHECK: name: noArgRetVoid
45
; CHECK: RTS
56
define void @noArgRetVoid() {
67
ret void
78
}
9+
10+
%struct.A = type { i8, float, i32, i32, i32 }
11+
12+
define void @test_arg_lowering1(i8 %x, i8 %y) {
13+
; CHECK-LABEL: name: test_arg_lowering1
14+
; CHECK: bb.1 (%ir-block.0):
15+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
16+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
17+
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
18+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
19+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
20+
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
21+
; CHECK: RTS
22+
ret void
23+
}
24+
25+
define void @test_arg_lowering2(i16 %x, i16 %y) {
26+
; CHECK-LABEL: name: test_arg_lowering2
27+
; CHECK: bb.1 (%ir-block.0):
28+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
29+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
30+
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD1]](s32)
31+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
32+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
33+
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD2]](s32)
34+
; CHECK: RTS
35+
ret void
36+
}
37+
38+
define void @test_arg_lowering3(i32 %x, i32 %y) {
39+
; CHECK-LABEL: name: test_arg_lowering3
40+
; CHECK: bb.1 (%ir-block.0):
41+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
42+
; CHECK: {{%.*}} G_LOAD [[G_F_I1]](p0)
43+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
44+
; CHECK: {{%.*}} G_LOAD [[G_F_I2]](p0)
45+
; CHECK: RTS
46+
ret void
47+
}
48+
49+
define void @test_arg_lowering_vector(<5 x i8> %x) {
50+
; CHECK-LABEL: name: test_arg_lowering_vector
51+
; CHECK: bb.1 (%ir-block.0):
52+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
53+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
54+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
55+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
56+
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
57+
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
58+
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
59+
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
60+
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
61+
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
62+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[G_LOAD1]](s32), [[G_LOAD2]](s32), [[G_LOAD3]](s32), [[G_LOAD4]](s32), [[G_LOAD5]](s32)
63+
; CHECK: [[G_TRUNC:%[0-9]+]]:_(<5 x s8>) = G_TRUNC [[BUILD_VECTOR]](<5 x s32>)
64+
; CHECK: RTS
65+
ret void
66+
}
67+
68+
define void @test_arg_lowering_array([5 x i8] %x) {
69+
; CHECK-LABEL: name: test_arg_lowering_array
70+
; CHECK: bb.1 (%ir-block.0):
71+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
72+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
73+
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
74+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
75+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
76+
; CHECK: [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
77+
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
78+
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
79+
; CHECK: [[G_TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD3]](s32)
80+
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
81+
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
82+
; CHECK: [[G_TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD4]](s32)
83+
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
84+
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
85+
; CHECK: [[G_TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD5]](s32)
86+
; CHECK: RTS
87+
ret void
88+
}
89+
90+
define void @test_arg_lowering_double(double %x) {
91+
; CHECK-LABEL: name: test_arg_lowering_double
92+
; CHECK: bb.1 (%ir-block.0):
93+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
94+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
95+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
96+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
97+
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
98+
; CHECK: RTS
99+
ret void
100+
}
101+
102+
define void @test_arg_lowering_float(float %x) {
103+
; CHECK-LABEL: name: test_arg_lowering_float
104+
; CHECK: bb.1 (%ir-block.0):
105+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
106+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
107+
; CHECK: RTS
108+
ret void
109+
}
110+
111+
define void @test_arg_lowering_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i128 %f){
112+
; CHECK-LABEL: name: test_arg_lowering_multiple
113+
; CHECK: bb.1 (%ir-block.0):
114+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
115+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
116+
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[G_LOAD1]](s32)
117+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
118+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
119+
; CHECK: [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
120+
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
121+
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
122+
; CHECK: [[G_TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD3]](s32)
123+
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
124+
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
125+
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
126+
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
127+
; CHECK: [[G_F_I6:%[0-9]+]]:_(p0) = G_FRAME_INDEX
128+
; CHECK: [[G_LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I6]](p0)
129+
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD5]](s32), [[G_LOAD6]](s32)
130+
; CHECK: [[G_F_I7:%[0-9]+]]:_(p0) = G_FRAME_INDEX
131+
; CHECK: [[G_LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I7]](p0)
132+
; CHECK: [[G_F_I8:%[0-9]+]]:_(p0) = G_FRAME_INDEX
133+
; CHECK: [[G_LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I8]](p0)
134+
; CHECK: [[G_F_I9:%[0-9]+]]:_(p0) = G_FRAME_INDEX
135+
; CHECK: [[G_LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I9]](p0)
136+
; CHECK: [[G_F_I10:%[0-9]+]]:_(p0) = G_FRAME_INDEX
137+
; CHECK: [[G_LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I10]](p0)
138+
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[G_LOAD7]](s32), [[G_LOAD8]](s32), [[G_LOAD9]](s32), [[G_LOAD10]](s32)
139+
; CHECK: RTS
140+
ret void
141+
}
142+
143+
define void @test_arg_lowering_ptr(i32* %x) {
144+
; CHECK-LABEL: name: test_arg_lowering_ptr
145+
; CHECK: bb.1 (%ir-block.0):
146+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
147+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
148+
; CHECK: RTS
149+
ret void
150+
}
151+
152+
define void @test_arg_lowering_float_ptr(float* %x) {
153+
; CHECK-LABEL: name: test_arg_lowering_float_ptr
154+
; CHECK: bb.1 (%ir-block.0):
155+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
156+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
157+
; CHECK: RTS
158+
ret void
159+
}
160+
161+
define void @test_arg_lowering_struct(%struct.A %a) #0 {
162+
; CHECK-LABEL: name: test_arg_lowering_struct
163+
; CHECK: bb.1 (%ir-block.0):
164+
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
165+
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
166+
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
167+
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
168+
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
169+
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
170+
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
171+
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
172+
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
173+
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
174+
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
175+
; CHECK: RTS
176+
ret void
177+
}

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