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Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
This reverts commit 1f161919065fbfa2b39b8f373553a64b89f826f8. We're seeing some issues with this internally. It seems that when the spill is created by register allocation, the GPR doesn't get allocated and an assertion fires during virtual register rewriting. The .mir test case contains the spill before register allocation so register allocation sees it as any other instruction.
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4 files changed

+22
-41
lines changed

4 files changed

+22
-41
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -287,10 +287,9 @@ bool RISCVExpandPseudo::expandVSPILL(MachineBasicBlock &MBB,
287287
const TargetRegisterInfo *TRI =
288288
MBB.getParent()->getSubtarget().getRegisterInfo();
289289
DebugLoc DL = MBBI->getDebugLoc();
290-
Register AddrInc = MBBI->getOperand(0).getReg();
291-
Register SrcReg = MBBI->getOperand(1).getReg();
292-
Register Base = MBBI->getOperand(2).getReg();
293-
Register VL = MBBI->getOperand(3).getReg();
290+
Register SrcReg = MBBI->getOperand(0).getReg();
291+
Register Base = MBBI->getOperand(1).getReg();
292+
Register VL = MBBI->getOperand(2).getReg();
294293
auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
295294
if (!ZvlssegInfo)
296295
return false;
@@ -319,12 +318,10 @@ bool RISCVExpandPseudo::expandVSPILL(MachineBasicBlock &MBB,
319318
.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
320319
.addReg(Base)
321320
.addMemOperand(*(MBBI->memoperands_begin()));
322-
if (I != NF - 1) {
323-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), AddrInc)
321+
if (I != NF - 1)
322+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
324323
.addReg(Base)
325324
.addReg(VL);
326-
Base = AddrInc;
327-
}
328325
}
329326
MBBI->eraseFromParent();
330327
return true;
@@ -336,9 +333,8 @@ bool RISCVExpandPseudo::expandVRELOAD(MachineBasicBlock &MBB,
336333
MBB.getParent()->getSubtarget().getRegisterInfo();
337334
DebugLoc DL = MBBI->getDebugLoc();
338335
Register DestReg = MBBI->getOperand(0).getReg();
339-
Register AddrInc = MBBI->getOperand(1).getReg();
340-
Register Base = MBBI->getOperand(2).getReg();
341-
Register VL = MBBI->getOperand(3).getReg();
336+
Register Base = MBBI->getOperand(1).getReg();
337+
Register VL = MBBI->getOperand(2).getReg();
342338
auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
343339
if (!ZvlssegInfo)
344340
return false;
@@ -367,12 +363,10 @@ bool RISCVExpandPseudo::expandVRELOAD(MachineBasicBlock &MBB,
367363
TRI->getSubReg(DestReg, SubRegIdx + I))
368364
.addReg(Base)
369365
.addMemOperand(*(MBBI->memoperands_begin()));
370-
if (I != NF - 1) {
371-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), AddrInc)
366+
if (I != NF - 1)
367+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
372368
.addReg(Base)
373369
.addReg(VL);
374-
Base = AddrInc;
375-
}
376370
}
377371
MBBI->eraseFromParent();
378372
return true;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -311,17 +311,10 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
311311
MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
312312

313313
MFI.setStackID(FI, TargetStackID::ScalableVector);
314-
auto MIB = BuildMI(MBB, I, DL, get(Opcode));
315-
if (IsZvlsseg) {
316-
// We need a GPR register to hold the incremented address for each subreg
317-
// after expansion.
318-
Register AddrInc =
319-
MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
320-
MIB.addReg(AddrInc, RegState::Define);
321-
}
322-
MIB.addReg(SrcReg, getKillRegState(IsKill))
323-
.addFrameIndex(FI)
324-
.addMemOperand(MMO);
314+
auto MIB = BuildMI(MBB, I, DL, get(Opcode))
315+
.addReg(SrcReg, getKillRegState(IsKill))
316+
.addFrameIndex(FI)
317+
.addMemOperand(MMO);
325318
if (IsZvlsseg) {
326319
// For spilling/reloading Zvlsseg registers, append the dummy field for
327320
// the scaled vector length. The argument will be used when expanding
@@ -412,15 +405,9 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
412405
MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
413406

414407
MFI.setStackID(FI, TargetStackID::ScalableVector);
415-
auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg);
416-
if (IsZvlsseg) {
417-
// We need a GPR register to hold the incremented address for each subreg
418-
// after expansion.
419-
Register AddrInc =
420-
MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
421-
MIB.addReg(AddrInc, RegState::Define);
422-
}
423-
MIB.addFrameIndex(FI).addMemOperand(MMO);
408+
auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg)
409+
.addFrameIndex(FI)
410+
.addMemOperand(MMO);
424411
if (IsZvlsseg) {
425412
// For spilling/reloading Zvlsseg registers, append the dummy field for
426413
// the scaled vector length. The argument will be used when expanding

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3498,11 +3498,11 @@ foreach lmul = MxList.m in {
34983498
defvar vreg = SegRegClass<lmul, nf>.RC;
34993499
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in {
35003500
def "PseudoVSPILL" # nf # "_" # lmul.MX :
3501-
Pseudo<(outs GPR:$addrinc), (ins vreg:$rs1, GPR:$rs2, GPR:$vlenb), []>;
3501+
Pseudo<(outs), (ins vreg:$rs1, GPR:$rs2, GPR:$vlenb), []>;
35023502
}
35033503
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1 in {
35043504
def "PseudoVRELOAD" # nf # "_" # lmul.MX :
3505-
Pseudo<(outs vreg:$rs1, GPR:$addrinc), (ins GPR:$rs2, GPR:$vlenb), []>;
3505+
Pseudo<(outs vreg:$rs1), (ins GPR:$rs2, GPR:$vlenb), []>;
35063506
}
35073507
}
35083508
}

‎llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,10 @@ body: |
3030
; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 renamable $x10, $noreg, 6, implicit $vl, implicit $vtype
3131
; CHECK-NEXT: $x11 = ADDI $x2, 16
3232
; CHECK-NEXT: $x12 = PseudoReadVLENB
33-
; CHECK-NEXT: dead renamable $x11 = PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, killed $x11, killed $x12
33+
; CHECK-NEXT: PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, killed $x11, killed $x12
3434
; CHECK-NEXT: $x11 = ADDI $x2, 16
3535
; CHECK-NEXT: $x12 = PseudoReadVLENB
36-
; CHECK-NEXT: dead renamable $v7_v8_v9_v10_v11_v12_v13, dead renamable $x11 = PseudoVRELOAD7_M1 killed $x11, killed $x12, implicit-def $v8
36+
; CHECK-NEXT: dead renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 killed $x11, killed $x12, implicit-def $v8
3737
; CHECK-NEXT: VS1R_V killed $v8, killed renamable $x10
3838
; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
3939
; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3
@@ -43,8 +43,8 @@ body: |
4343
%0:gpr = COPY $x10
4444
%1:gprnox0 = COPY $x11
4545
$v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 %0, %1, 6
46-
%2:gpr = PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0, $x0
47-
renamable $v7_v8_v9_v10_v11_v12_v13, %3:gpr = PseudoVRELOAD7_M1 %stack.0, $x0
46+
PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0, $x0
47+
renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 %stack.0, $x0
4848
VS1R_V killed $v8, %0:gpr
4949
PseudoRET
5050
...

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