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[docs] Fix typos
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llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst

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@@ -96,7 +96,7 @@ compiler [:ref:`GCC <amdgpu-dwarf-GCC>`] and the Perforce TotalView HPC debugger
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[:ref:`Perforce-TotalView <amdgpu-dwarf-Perforce-TotalView>`].
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However, the extensions are intended to be vendor and architecture neutral. They
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are believed to apply to other heterogenous hardware devices including GPUs,
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are believed to apply to other heterogeneous hardware devices including GPUs,
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DSPs, FPGAs, and other specialized hardware. These collectively include similar
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characteristics and requirements as AMDGPU devices. Some of the extension can
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also apply to traditional CPU hardware that supports large vector registers.
@@ -2068,7 +2068,7 @@ register starting at the specified bit offset.
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*An implementation may evaluate the call frame information immediately, or
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may defer evaluation until L is accessed by an operation. If evaluation is
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defered, R and the current context can be recorded in L. When accessed, the
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deferred, R and the current context can be recorded in L. When accessed, the
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recorded context is used to evaluate the call frame information, not the
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current context of the access operation.*
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llvm/docs/AMDGPUUsage.rst

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@@ -1139,7 +1139,7 @@ The loaded code object path URI syntax is defined by the following BNF syntax:
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**file_path**
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Is the file's path specified as a URI encoded UTF-8 string. In URI encoding,
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every character that is not in the regular expression ``[a-zA-Z0-9/_.~-]`` is
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encoded as two uppercase hexidecimal digits proceeded by "%". Directories in
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encoded as two uppercase hexadecimal digits proceeded by "%". Directories in
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the path are separated by "/".
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**offset**
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VGPR232-239
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VGPR248-255
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*Except the argument registers, the VGPR cloberred and the preserved
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*Except the argument registers, the VGPR clobbered and the preserved
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registers are intermixed at regular intervals in order to
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get a better occupancy.*
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llvm/docs/AliasAnalysis.rst

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@@ -81,7 +81,7 @@ In this case, the ``basic-aa`` pass will disambiguate the stores to ``C[0]`` and
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``C[1]`` because they are accesses to two distinct locations one byte apart, and
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the accesses are each one byte. In this case, the Loop Invariant Code Motion
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(LICM) pass can use store motion to remove the stores from the loop. In
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constrast, the following code:
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contrast, the following code:
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.. code-block:: c++
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llvm/docs/BugLifeCycle.rst

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@@ -116,7 +116,7 @@ Examples of reasons for resolving are:
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clearly understand the problem being reported (e.g. not reproducible). It is
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fine to resolve such a bug e.g. with resolution WORKSFORME and leaving a
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comment to encourage the reporter to reopen the bug with more information
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if it's still reproducable on their end.
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if it's still reproducible on their end.
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If a bug is resolved, please fill in the revision number it was fixed in in the
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"Fixed by Commit(s)" field.

llvm/docs/CMake.rst

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@@ -447,7 +447,7 @@ LLVM-specific variables
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**LLVM_STATIC_LINK_CXX_STDLIB**:BOOL
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Statically link to the C++ standard library if possible. This uses the flag
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"-static-libstdc++", but a Clang host compiler will statically link to libc++
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if used in conjuction with the **LLVM_ENABLE_LIBCXX** flag. Defaults to OFF.
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if used in conjunction with the **LLVM_ENABLE_LIBCXX** flag. Defaults to OFF.
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**LLVM_ENABLE_LLD**:BOOL
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This option is equivalent to `-DLLVM_USE_LINKER=lld`, except during a 2-stage

llvm/docs/CommandGuide/llvm-extract.rst

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@@ -39,7 +39,7 @@ OPTIONS
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**--bb** *basic-block-specifier*
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Extract basic blocks(s) specicified in *basic-block-specifier*. May be
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Extract basic blocks(s) specified in *basic-block-specifier*. May be
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specified multiple times. Each <function:bb[;bb]> specifier pair will create
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a function. If multiple basic blocks are specified in one pair, the first
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block in the sequence should dominate the rest.

llvm/docs/ExceptionHandling.rst

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@@ -530,7 +530,7 @@ on Itanium C++ ABI platforms. The fundamental difference between the two models
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is that Itanium EH is designed around the idea of "successive unwinding," while
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Windows EH is not.
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Under Itanium, throwing an exception typically involes allocating thread local
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Under Itanium, throwing an exception typically involves allocating thread local
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memory to hold the exception, and calling into the EH runtime. The runtime
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identifies frames with appropriate exception handling actions, and successively
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resets the register context of the current thread to the most recently active

llvm/docs/GlobalISel/GMIR.rst

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@@ -104,7 +104,7 @@ In practice, register files A and B are rarely equal. They can typically store
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the same data but there's usually some restrictions on what operations you can
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do on each register file. A fairly common pattern is for one of them to be
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accessible to integer operations and the other accessible to floating point
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operations. To accomodate this, let's rename A and B to GPR (general purpose
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operations. To accommodate this, let's rename A and B to GPR (general purpose
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registers) and FPR (floating point registers).
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We now have some additional constraints that limit us. An operation like G_FMUL

llvm/docs/GlobalISel/GenericOpcode.rst

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@@ -153,7 +153,7 @@ G_BITCAST
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^^^^^^^^^
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Reinterpret a value as a new type. This is usually done without
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changing any bits but this is not always the case due a sublety in the
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changing any bits but this is not always the case due a subtlety in the
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definition of the :ref:`LLVM-IR Bitcast Instruction <i_bitcast>`. It
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is allowed to bitcast between pointers with the same size, but
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different address spaces.

llvm/docs/HowToSetUpLLVMStyleRTTI.rst

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@@ -430,7 +430,7 @@ template argument and the parent class as the second argument. Any class that
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uses ``RTTIExtends`` must define a ``static char ID`` member, the address of
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which will be used to identify the type.
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This open-hierarchy RTTI support should only be used if your use case requries
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This open-hierarchy RTTI support should only be used if your use case requires
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it. Otherwise the standard LLVM RTTI system should be preferred.
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.. _`Curiously Recurring Template Idiom`:

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