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kazutakahiratamemfrob
kazutakahirata
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memfrob
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[Target] Migrate from getNumArgOperands to arg_size (NFC)
Note that getNumArgOperands is considered a legacy name. See llvm/include/llvm/IR/InstrTypes.h for details.
1 parent 7d8fac3 commit c421a98

13 files changed

+35
-35
lines changed

‎llvm/lib/Target/AArch64/AArch64FastISel.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3483,7 +3483,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
34833483
return false;
34843484

34853485
const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
3486-
return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
3486+
return lowerCallTo(II, IntrMemName, II->arg_size() - 1);
34873487
}
34883488
case Intrinsic::memset: {
34893489
const MemSetInst *MSI = cast<MemSetInst>(II);
@@ -3499,7 +3499,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
34993499
// address spaces.
35003500
return false;
35013501

3502-
return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
3502+
return lowerCallTo(II, "memset", II->arg_size() - 1);
35033503
}
35043504
case Intrinsic::sin:
35053505
case Intrinsic::cos:
@@ -3533,7 +3533,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
35333533
}
35343534

35353535
ArgListTy Args;
3536-
Args.reserve(II->getNumArgOperands());
3536+
Args.reserve(II->arg_size());
35373537

35383538
// Populate the argument list.
35393539
for (auto &Arg : II->args()) {

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11323,7 +11323,7 @@ setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL,
1132311323
// memVT is `NumVecs * VT`.
1132411324
Info.memVT = EVT::getVectorVT(CI.getType()->getContext(), VT.getScalarType(),
1132511325
EC * NumVecs);
11326-
Info.ptrVal = CI.getArgOperand(CI.getNumArgOperands() - 1);
11326+
Info.ptrVal = CI.getArgOperand(CI.arg_size() - 1);
1132711327
Info.offset = 0;
1132811328
Info.align.reset();
1132911329
Info.flags = MachineMemOperand::MOStore;
@@ -11361,7 +11361,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1136111361
// Conservatively set memVT to the entire set of vectors loaded.
1136211362
uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
1136311363
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11364-
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
11364+
Info.ptrVal = I.getArgOperand(I.arg_size() - 1);
1136511365
Info.offset = 0;
1136611366
Info.align.reset();
1136711367
// volatile loads with NEON intrinsics not supported
@@ -11380,14 +11380,14 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1138011380
Info.opc = ISD::INTRINSIC_VOID;
1138111381
// Conservatively set memVT to the entire set of vectors stored.
1138211382
unsigned NumElts = 0;
11383-
for (unsigned ArgI = 0, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11384-
Type *ArgTy = I.getArgOperand(ArgI)->getType();
11383+
for (const Value *Arg : I.args()) {
11384+
Type *ArgTy = Arg->getType();
1138511385
if (!ArgTy->isVectorTy())
1138611386
break;
1138711387
NumElts += DL.getTypeSizeInBits(ArgTy) / 64;
1138811388
}
1138911389
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11390-
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
11390+
Info.ptrVal = I.getArgOperand(I.arg_size() - 1);
1139111391
Info.offset = 0;
1139211392
Info.align.reset();
1139311393
// volatile stores with NEON intrinsics not supported

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1862,7 +1862,7 @@ Value *AArch64TTIImpl::getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
18621862
StructType *ST = dyn_cast<StructType>(ExpectedType);
18631863
if (!ST)
18641864
return nullptr;
1865-
unsigned NumElts = Inst->getNumArgOperands() - 1;
1865+
unsigned NumElts = Inst->arg_size() - 1;
18661866
if (ST->getNumElements() != NumElts)
18671867
return nullptr;
18681868
for (unsigned i = 0, e = NumElts; i != e; ++i) {
@@ -1903,7 +1903,7 @@ bool AArch64TTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
19031903
case Intrinsic::aarch64_neon_st4:
19041904
Info.ReadMem = false;
19051905
Info.WriteMem = true;
1906-
Info.PtrVal = Inst->getArgOperand(Inst->getNumArgOperands() - 1);
1906+
Info.PtrVal = Inst->getArgOperand(Inst->arg_size() - 1);
19071907
break;
19081908
}
19091909

‎llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -567,7 +567,7 @@ bool AMDGPULibCalls::fold_read_write_pipe(CallInst *CI, IRBuilder<> &B,
567567
auto *M = Callee->getParent();
568568
auto &Ctx = M->getContext();
569569
std::string Name = std::string(Callee->getName());
570-
auto NumArg = CI->getNumArgOperands();
570+
auto NumArg = CI->arg_size();
571571
if (NumArg != 4 && NumArg != 6)
572572
return false;
573573
auto *PacketSize = CI->getArgOperand(NumArg - 2);
@@ -584,7 +584,7 @@ bool AMDGPULibCalls::fold_read_write_pipe(CallInst *CI, IRBuilder<> &B,
584584
PtrElemTy = Type::getIntNTy(Ctx, Size * 8);
585585
else
586586
PtrElemTy = FixedVectorType::get(Type::getInt64Ty(Ctx), Size / 8);
587-
unsigned PtrArgLoc = CI->getNumArgOperands() - 3;
587+
unsigned PtrArgLoc = CI->arg_size() - 3;
588588
auto PtrArg = CI->getArgOperand(PtrArgLoc);
589589
unsigned PtrArgAS = PtrArg->getType()->getPointerAddressSpace();
590590
auto *PtrTy = llvm::PointerType::get(PtrElemTy, PtrArgAS);
@@ -648,7 +648,7 @@ bool AMDGPULibCalls::fold(CallInst *CI, AliasAnalysis *AA) {
648648
return false;
649649

650650
// Further check the number of arguments to see if they match.
651-
if (CI->getNumArgOperands() != FInfo.getNumArgs())
651+
if (CI->arg_size() != FInfo.getNumArgs())
652652
return false;
653653

654654
if (TDOFold(CI, FInfo))
@@ -1606,7 +1606,7 @@ bool AMDGPULibCalls::evaluateScalarMathFunc(FuncInfo &FInfo,
16061606
}
16071607

16081608
bool AMDGPULibCalls::evaluateCall(CallInst *aCI, FuncInfo &FInfo) {
1609-
int numArgs = (int)aCI->getNumArgOperands();
1609+
int numArgs = (int)aCI->arg_size();
16101610
if (numArgs > 3)
16111611
return false;
16121612

‎llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ bool AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(Module &M) {
153153
const char NonLiteralStr[4] = "???";
154154

155155
for (auto CI : Printfs) {
156-
unsigned NumOps = CI->getNumArgOperands();
156+
unsigned NumOps = CI->arg_size();
157157

158158
SmallString<16> OpConvSpecifiers;
159159
Value *Op = CI->getArgOperand(0);
@@ -201,10 +201,10 @@ bool AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(Module &M) {
201201
std::string AStreamHolder;
202202
raw_string_ostream Sizes(AStreamHolder);
203203
int Sum = DWORD_ALIGN;
204-
Sizes << CI->getNumArgOperands() - 1;
204+
Sizes << CI->arg_size() - 1;
205205
Sizes << ':';
206-
for (unsigned ArgCount = 1; ArgCount < CI->getNumArgOperands() &&
207-
ArgCount <= OpConvSpecifiers.size();
206+
for (unsigned ArgCount = 1;
207+
ArgCount < CI->arg_size() && ArgCount <= OpConvSpecifiers.size();
208208
ArgCount++) {
209209
Value *Arg = CI->getArgOperand(ArgCount);
210210
Type *ArgType = Arg->getType();
@@ -389,8 +389,8 @@ bool AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(Module &M) {
389389

390390
Type *Int32Ty = Type::getInt32Ty(Ctx);
391391
Type *Int64Ty = Type::getInt64Ty(Ctx);
392-
for (unsigned ArgCount = 1; ArgCount < CI->getNumArgOperands() &&
393-
ArgCount <= OpConvSpecifiers.size();
392+
for (unsigned ArgCount = 1;
393+
ArgCount < CI->arg_size() && ArgCount <= OpConvSpecifiers.size();
394394
ArgCount++) {
395395
Value *Arg = CI->getArgOperand(ArgCount);
396396
Type *ArgType = Arg->getType();
@@ -524,7 +524,7 @@ bool AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(Module &M) {
524524
LLVM_DEBUG(dbgs() << "inserting store to printf buffer:\n"
525525
<< *StBuff << '\n');
526526
(void)StBuff;
527-
if (I + 1 == E && ArgCount + 1 == CI->getNumArgOperands())
527+
if (I + 1 == E && ArgCount + 1 == CI->arg_size())
528528
break;
529529
BufferIdx = GetElementPtrInst::Create(I8Ty, BufferIdx, BuffOffset,
530530
"PrintBuffNextPtr", Brnch);

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -20081,7 +20081,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
2008120081
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
2008220082
Info.ptrVal = I.getArgOperand(0);
2008320083
Info.offset = 0;
20084-
Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
20084+
Value *AlignArg = I.getArgOperand(I.arg_size() - 1);
2008520085
Info.align = cast<ConstantInt>(AlignArg)->getMaybeAlignValue();
2008620086
// volatile loads with NEON intrinsics not supported
2008720087
Info.flags = MachineMemOperand::MOLoad;
@@ -20095,7 +20095,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
2009520095
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
2009620096
uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
2009720097
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
20098-
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
20098+
Info.ptrVal = I.getArgOperand(I.arg_size() - 1);
2009920099
Info.offset = 0;
2010020100
Info.align.reset();
2010120101
// volatile loads with NEON intrinsics not supported
@@ -20113,7 +20113,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
2011320113
// Conservatively set memVT to the entire set of vectors stored.
2011420114
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
2011520115
unsigned NumElts = 0;
20116-
for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
20116+
for (unsigned ArgI = 1, ArgE = I.arg_size(); ArgI < ArgE; ++ArgI) {
2011720117
Type *ArgTy = I.getArgOperand(ArgI)->getType();
2011820118
if (!ArgTy->isVectorTy())
2011920119
break;
@@ -20122,7 +20122,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
2012220122
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
2012320123
Info.ptrVal = I.getArgOperand(0);
2012420124
Info.offset = 0;
20125-
Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
20125+
Value *AlignArg = I.getArgOperand(I.arg_size() - 1);
2012620126
Info.align = cast<ConstantInt>(AlignArg)->getMaybeAlignValue();
2012720127
// volatile stores with NEON intrinsics not supported
2012820128
Info.flags = MachineMemOperand::MOStore;
@@ -20135,7 +20135,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
2013520135
// Conservatively set memVT to the entire set of vectors stored.
2013620136
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
2013720137
unsigned NumElts = 0;
20138-
for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
20138+
for (unsigned ArgI = 1, ArgE = I.arg_size(); ArgI < ArgE; ++ArgI) {
2013920139
Type *ArgTy = I.getArgOperand(ArgI)->getType();
2014020140
if (!ArgTy->isVectorTy())
2014120141
break;

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ ARMTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
149149
Align MemAlign =
150150
getKnownAlignment(II.getArgOperand(0), IC.getDataLayout(), &II,
151151
&IC.getAssumptionCache(), &IC.getDominatorTree());
152-
unsigned AlignArg = II.getNumArgOperands() - 1;
152+
unsigned AlignArg = II.arg_size() - 1;
153153
Value *AlignArgOp = II.getArgOperand(AlignArg);
154154
MaybeAlign Align = cast<ConstantInt>(AlignArgOp)->getMaybeAlignValue();
155155
if (Align && *Align < MemAlign) {

‎llvm/lib/Target/Mips/MipsFastISel.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1660,7 +1660,7 @@ bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
16601660
if (!MTI->getLength()->getType()->isIntegerTy(32))
16611661
return false;
16621662
const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1663-
return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1663+
return lowerCallTo(II, IntrMemName, II->arg_size() - 1);
16641664
}
16651665
case Intrinsic::memset: {
16661666
const MemSetInst *MSI = cast<MemSetInst>(II);
@@ -1669,7 +1669,7 @@ bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
16691669
return false;
16701670
if (!MSI->getLength()->getType()->isIntegerTy(32))
16711671
return false;
1672-
return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1672+
return lowerCallTo(II, "memset", II->arg_size() - 1);
16731673
}
16741674
}
16751675
return false;

‎llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -822,7 +822,7 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) {
822822
}
823823

824824
SmallVector<unsigned, 8> Args;
825-
for (unsigned I = 0, E = Call->getNumArgOperands(); I < E; ++I) {
825+
for (unsigned I = 0, E = Call->arg_size(); I < E; ++I) {
826826
Value *V = Call->getArgOperand(I);
827827
MVT::SimpleValueType ArgTy = getSimpleType(V->getType());
828828
if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)

‎llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -549,7 +549,7 @@ Value *WebAssemblyLowerEmscriptenEHSjLj::wrapInvoke(CallBase *CI) {
549549
// No attributes for the callee pointer.
550550
ArgAttributes.push_back(AttributeSet());
551551
// Copy the argument attributes from the original
552-
for (unsigned I = 0, E = CI->getNumArgOperands(); I < E; ++I)
552+
for (unsigned I = 0, E = CI->arg_size(); I < E; ++I)
553553
ArgAttributes.push_back(InvokeAL.getParamAttrs(I));
554554

555555
AttrBuilder FnAttrs(InvokeAL.getFnAttrs());

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