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[test] refresh a couple of autogen tests
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‎llvm/test/CodeGen/AMDGPU/multilevel-break.ll

Lines changed: 26 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
32
; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
43
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
54

@@ -26,7 +25,7 @@ define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
2625
; OPT: Flow:
2726
; OPT-NEXT: [[TMP4]] = phi i32 [ [[TMP47]], [[ENDIF]] ], [ [[TMP0]], [[LOOP]] ]
2827
; OPT-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP51:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
29-
; OPT-NEXT: [[TMP6:%.*]] = phi i1 [ [[TMP11:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
28+
; OPT-NEXT: [[TMP6:%.*]] = phi i1 [ [[TMP51_INV:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
3029
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP3]])
3130
; OPT-NEXT: [[TMP7]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP6]], i64 [[PHI_BROKEN]])
3231
; OPT-NEXT: [[TMP8:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP7]])
@@ -41,7 +40,7 @@ define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
4140
; OPT-NEXT: ret void
4241
; OPT: ENDIF:
4342
; OPT-NEXT: [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]]
44-
; OPT-NEXT: [[TMP11]] = xor i1 [[TMP51]], true
43+
; OPT-NEXT: [[TMP51_INV]] = xor i1 [[TMP51]], true
4544
; OPT-NEXT: br label [[FLOW]]
4645
;
4746
; GCN-LABEL: multi_else_break:
@@ -117,61 +116,61 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
117116
; OPT-NEXT: [[TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
118117
; OPT-NEXT: br label [[BB1:%.*]]
119118
; OPT: bb1:
120-
; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP5:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ]
119+
; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP4:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ]
121120
; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW4]] ]
122121
; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
123122
; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
124123
; OPT-NEXT: [[LOAD0:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
125124
; OPT-NEXT: br label [[NODEBLOCK:%.*]]
126125
; OPT: NodeBlock:
127126
; OPT-NEXT: [[PIVOT:%.*]] = icmp slt i32 [[LOAD0]], 1
128-
; OPT-NEXT: [[TMP0:%.*]] = xor i1 [[PIVOT]], true
129-
; OPT-NEXT: br i1 [[TMP0]], label [[LEAFBLOCK1:%.*]], label [[FLOW:%.*]]
127+
; OPT-NEXT: [[PIVOT_INV:%.*]] = xor i1 [[PIVOT]], true
128+
; OPT-NEXT: br i1 [[PIVOT_INV]], label [[LEAFBLOCK1:%.*]], label [[FLOW:%.*]]
130129
; OPT: LeafBlock1:
131130
; OPT-NEXT: [[SWITCHLEAF2:%.*]] = icmp eq i32 [[LOAD0]], 1
132131
; OPT-NEXT: br i1 [[SWITCHLEAF2]], label [[CASE1:%.*]], label [[FLOW3:%.*]]
133132
; OPT: Flow3:
134-
; OPT-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP11:%.*]], [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
135-
; OPT-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
133+
; OPT-NEXT: [[TMP0:%.*]] = phi i1 [ [[CMP2_INV:%.*]], [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
134+
; OPT-NEXT: [[TMP1:%.*]] = phi i1 [ false, [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
136135
; OPT-NEXT: br label [[FLOW]]
137136
; OPT: LeafBlock:
138137
; OPT-NEXT: [[SWITCHLEAF:%.*]] = icmp eq i32 [[LOAD0]], 0
139138
; OPT-NEXT: br i1 [[SWITCHLEAF]], label [[CASE0:%.*]], label [[FLOW5:%.*]]
140139
; OPT: Flow4:
141-
; OPT-NEXT: [[TMP3:%.*]] = phi i1 [ [[TMP12:%.*]], [[FLOW5]] ], [ [[TMP8:%.*]], [[FLOW]] ]
142-
; OPT-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP13:%.*]], [[FLOW5]] ], [ [[TMP9:%.*]], [[FLOW]] ]
143-
; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP3]], i64 [[PHI_BROKEN]])
144-
; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]])
145-
; OPT-NEXT: br i1 [[TMP6]], label [[FLOW6:%.*]], label [[BB1]]
140+
; OPT-NEXT: [[TMP2:%.*]] = phi i1 [ [[TMP9:%.*]], [[FLOW5]] ], [ [[TMP6:%.*]], [[FLOW]] ]
141+
; OPT-NEXT: [[TMP3:%.*]] = phi i1 [ [[TMP10:%.*]], [[FLOW5]] ], [ [[TMP7:%.*]], [[FLOW]] ]
142+
; OPT-NEXT: [[TMP4]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP2]], i64 [[PHI_BROKEN]])
143+
; OPT-NEXT: [[TMP5:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP4]])
144+
; OPT-NEXT: br i1 [[TMP5]], label [[FLOW6:%.*]], label [[BB1]]
146145
; OPT: case0:
147146
; OPT-NEXT: [[LOAD1:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
148147
; OPT-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP]], [[LOAD1]]
149-
; OPT-NEXT: [[TMP7:%.*]] = xor i1 [[CMP1]], true
148+
; OPT-NEXT: [[CMP1_INV:%.*]] = xor i1 [[CMP1]], true
150149
; OPT-NEXT: br label [[FLOW5]]
151150
; OPT: Flow:
152-
; OPT-NEXT: [[TMP8]] = phi i1 [ [[TMP1]], [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
153-
; OPT-NEXT: [[TMP9]] = phi i1 [ [[TMP2]], [[FLOW3]] ], [ false, [[NODEBLOCK]] ]
154-
; OPT-NEXT: [[TMP10:%.*]] = phi i1 [ false, [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
155-
; OPT-NEXT: br i1 [[TMP10]], label [[LEAFBLOCK:%.*]], label [[FLOW4]]
151+
; OPT-NEXT: [[TMP6]] = phi i1 [ [[TMP0]], [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
152+
; OPT-NEXT: [[TMP7]] = phi i1 [ [[TMP1]], [[FLOW3]] ], [ false, [[NODEBLOCK]] ]
153+
; OPT-NEXT: [[TMP8:%.*]] = phi i1 [ false, [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
154+
; OPT-NEXT: br i1 [[TMP8]], label [[LEAFBLOCK:%.*]], label [[FLOW4]]
156155
; OPT: case1:
157156
; OPT-NEXT: [[LOAD2:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
158157
; OPT-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP]], [[LOAD2]]
159-
; OPT-NEXT: [[TMP11]] = xor i1 [[CMP2]], true
158+
; OPT-NEXT: [[CMP2_INV]] = xor i1 [[CMP2]], true
160159
; OPT-NEXT: br label [[FLOW3]]
161160
; OPT: Flow5:
162-
; OPT-NEXT: [[TMP12]] = phi i1 [ [[TMP7]], [[CASE0]] ], [ [[TMP8]], [[LEAFBLOCK]] ]
163-
; OPT-NEXT: [[TMP13]] = phi i1 [ false, [[CASE0]] ], [ true, [[LEAFBLOCK]] ]
161+
; OPT-NEXT: [[TMP9]] = phi i1 [ [[CMP1_INV]], [[CASE0]] ], [ [[TMP6]], [[LEAFBLOCK]] ]
162+
; OPT-NEXT: [[TMP10]] = phi i1 [ false, [[CASE0]] ], [ true, [[LEAFBLOCK]] ]
164163
; OPT-NEXT: br label [[FLOW4]]
165164
; OPT: Flow6:
166-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]])
167-
; OPT-NEXT: [[TMP14:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP4]])
168-
; OPT-NEXT: [[TMP15:%.*]] = extractvalue { i1, i64 } [[TMP14]], 0
169-
; OPT-NEXT: [[TMP16:%.*]] = extractvalue { i1, i64 } [[TMP14]], 1
170-
; OPT-NEXT: br i1 [[TMP15]], label [[NEWDEFAULT:%.*]], label [[BB9:%.*]]
165+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP4]])
166+
; OPT-NEXT: [[TMP11:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP3]])
167+
; OPT-NEXT: [[TMP12:%.*]] = extractvalue { i1, i64 } [[TMP11]], 0
168+
; OPT-NEXT: [[TMP13:%.*]] = extractvalue { i1, i64 } [[TMP11]], 1
169+
; OPT-NEXT: br i1 [[TMP12]], label [[NEWDEFAULT:%.*]], label [[BB9:%.*]]
171170
; OPT: NewDefault:
172171
; OPT-NEXT: br label [[BB9]]
173172
; OPT: bb9:
174-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP16]])
173+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP13]])
175174
; OPT-NEXT: ret void
176175
;
177176
; GCN-LABEL: multi_if_break_loop:

‎llvm/test/Transforms/LoopVectorize/loop-form.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,8 +1071,8 @@ define void @scalar_predication(float* %addr) {
10711071
; CHECK: pred.store.continue2:
10721072
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
10731073
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
1074-
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
1075-
; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
1074+
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
1075+
; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
10761076
; CHECK: middle.block:
10771077
; CHECK-NEXT: br label [[SCALAR_PH]]
10781078
; CHECK: scalar.ph:
@@ -1084,8 +1084,8 @@ define void @scalar_predication(float* %addr) {
10841084
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], 200
10851085
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP_BODY:%.*]]
10861086
; CHECK: loop.body:
1087-
; CHECK-NEXT: [[TMP11:%.*]] = load float, float* [[GEP]], align 4
1088-
; CHECK-NEXT: [[PRED:%.*]] = fcmp oeq float [[TMP11]], 0.000000e+00
1087+
; CHECK-NEXT: [[TMP12:%.*]] = load float, float* [[GEP]], align 4
1088+
; CHECK-NEXT: [[PRED:%.*]] = fcmp oeq float [[TMP12]], 0.000000e+00
10891089
; CHECK-NEXT: br i1 [[PRED]], label [[LOOP_LATCH]], label [[THEN:%.*]]
10901090
; CHECK: then:
10911091
; CHECK-NEXT: store float 1.000000e+01, float* [[GEP]], align 4

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