Skip to content

Commit d7f56a0

Browse files
lei137memfrob
lei137
authored and
memfrob
committed
[PowerPC][NFC] Cleanup load/store spilling code
Summary: Cleanup and commonize code used for spilling to the stack. Reviewers: stefanp, nemanjai, #powerpc, kamaub Reviewed By: nemanjai, #powerpc, kamaub Subscribers: kamaub, hiraditya, wuzish, shchenz, llvm-commits, kbarton Tags: #llvm, #powerpc Differential Revision: https://reviews.llvm.org/D79736
1 parent 5dfe98c commit d7f56a0

File tree

3 files changed

+122
-216
lines changed

3 files changed

+122
-216
lines changed

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 53 additions & 211 deletions
Original file line numberDiff line numberDiff line change
@@ -72,27 +72,6 @@ static cl::opt<bool>
7272
UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
7373
cl::desc("Use the old (incorrect) instruction latency calculation"));
7474

75-
// Index into the OpcodesForSpill array.
76-
enum SpillOpcodeKey {
77-
SOK_Int4Spill,
78-
SOK_Int8Spill,
79-
SOK_Float8Spill,
80-
SOK_Float4Spill,
81-
SOK_CRSpill,
82-
SOK_CRBitSpill,
83-
SOK_VRVectorSpill,
84-
SOK_VSXVectorSpill,
85-
SOK_VectorFloat8Spill,
86-
SOK_VectorFloat4Spill,
87-
SOK_VRSaveSpill,
88-
SOK_QuadFloat8Spill,
89-
SOK_QuadFloat4Spill,
90-
SOK_QuadBitSpill,
91-
SOK_SpillToVSR,
92-
SOK_SPESpill,
93-
SOK_LastOpcodeSpill // This must be last on the enum.
94-
};
95-
9675
// Pin the vtable to this file.
9776
void PPCInstrInfo::anchor() {}
9877

@@ -1050,183 +1029,66 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
10501029
BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
10511030
}
10521031

1053-
unsigned PPCInstrInfo::getStoreOpcodeForSpill(unsigned Reg,
1054-
const TargetRegisterClass *RC)
1055-
const {
1056-
const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1032+
static unsigned getSpillIndex(const TargetRegisterClass *RC) {
10571033
int OpcodeIndex = 0;
10581034

1059-
if (RC != nullptr) {
1060-
if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1061-
PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1062-
OpcodeIndex = SOK_Int4Spill;
1063-
} else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1064-
PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1065-
OpcodeIndex = SOK_Int8Spill;
1066-
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1067-
OpcodeIndex = SOK_Float8Spill;
1068-
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1069-
OpcodeIndex = SOK_Float4Spill;
1070-
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1071-
OpcodeIndex = SOK_SPESpill;
1072-
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1073-
OpcodeIndex = SOK_CRSpill;
1074-
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1075-
OpcodeIndex = SOK_CRBitSpill;
1076-
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1077-
OpcodeIndex = SOK_VRVectorSpill;
1078-
} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1079-
OpcodeIndex = SOK_VSXVectorSpill;
1080-
} else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1081-
OpcodeIndex = SOK_VectorFloat8Spill;
1082-
} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1083-
OpcodeIndex = SOK_VectorFloat4Spill;
1084-
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1085-
OpcodeIndex = SOK_VRSaveSpill;
1086-
} else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1087-
OpcodeIndex = SOK_QuadFloat8Spill;
1088-
} else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1089-
OpcodeIndex = SOK_QuadFloat4Spill;
1090-
} else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1091-
OpcodeIndex = SOK_QuadBitSpill;
1092-
} else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1093-
OpcodeIndex = SOK_SpillToVSR;
1094-
} else {
1095-
llvm_unreachable("Unknown regclass!");
1096-
}
1035+
if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1036+
PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1037+
OpcodeIndex = SOK_Int4Spill;
1038+
} else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1039+
PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1040+
OpcodeIndex = SOK_Int8Spill;
1041+
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1042+
OpcodeIndex = SOK_Float8Spill;
1043+
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1044+
OpcodeIndex = SOK_Float4Spill;
1045+
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1046+
OpcodeIndex = SOK_SPESpill;
1047+
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1048+
OpcodeIndex = SOK_CRSpill;
1049+
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1050+
OpcodeIndex = SOK_CRBitSpill;
1051+
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1052+
OpcodeIndex = SOK_VRVectorSpill;
1053+
} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1054+
OpcodeIndex = SOK_VSXVectorSpill;
1055+
} else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1056+
OpcodeIndex = SOK_VectorFloat8Spill;
1057+
} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1058+
OpcodeIndex = SOK_VectorFloat4Spill;
1059+
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1060+
OpcodeIndex = SOK_VRSaveSpill;
1061+
} else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1062+
OpcodeIndex = SOK_QuadFloat8Spill;
1063+
} else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1064+
OpcodeIndex = SOK_QuadFloat4Spill;
1065+
} else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1066+
OpcodeIndex = SOK_QuadBitSpill;
1067+
} else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1068+
OpcodeIndex = SOK_SpillToVSR;
10971069
} else {
1098-
if (PPC::GPRCRegClass.contains(Reg) ||
1099-
PPC::GPRC_NOR0RegClass.contains(Reg)) {
1100-
OpcodeIndex = SOK_Int4Spill;
1101-
} else if (PPC::G8RCRegClass.contains(Reg) ||
1102-
PPC::G8RC_NOX0RegClass.contains(Reg)) {
1103-
OpcodeIndex = SOK_Int8Spill;
1104-
} else if (PPC::F8RCRegClass.contains(Reg)) {
1105-
OpcodeIndex = SOK_Float8Spill;
1106-
} else if (PPC::F4RCRegClass.contains(Reg)) {
1107-
OpcodeIndex = SOK_Float4Spill;
1108-
} else if (PPC::SPERCRegClass.contains(Reg)) {
1109-
OpcodeIndex = SOK_SPESpill;
1110-
} else if (PPC::CRRCRegClass.contains(Reg)) {
1111-
OpcodeIndex = SOK_CRSpill;
1112-
} else if (PPC::CRBITRCRegClass.contains(Reg)) {
1113-
OpcodeIndex = SOK_CRBitSpill;
1114-
} else if (PPC::VRRCRegClass.contains(Reg)) {
1115-
OpcodeIndex = SOK_VRVectorSpill;
1116-
} else if (PPC::VSRCRegClass.contains(Reg)) {
1117-
OpcodeIndex = SOK_VSXVectorSpill;
1118-
} else if (PPC::VSFRCRegClass.contains(Reg)) {
1119-
OpcodeIndex = SOK_VectorFloat8Spill;
1120-
} else if (PPC::VSSRCRegClass.contains(Reg)) {
1121-
OpcodeIndex = SOK_VectorFloat4Spill;
1122-
} else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1123-
OpcodeIndex = SOK_VRSaveSpill;
1124-
} else if (PPC::QFRCRegClass.contains(Reg)) {
1125-
OpcodeIndex = SOK_QuadFloat8Spill;
1126-
} else if (PPC::QSRCRegClass.contains(Reg)) {
1127-
OpcodeIndex = SOK_QuadFloat4Spill;
1128-
} else if (PPC::QBRCRegClass.contains(Reg)) {
1129-
OpcodeIndex = SOK_QuadBitSpill;
1130-
} else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1131-
OpcodeIndex = SOK_SpillToVSR;
1132-
} else {
1133-
llvm_unreachable("Unknown regclass!");
1134-
}
1070+
llvm_unreachable("Unknown regclass!");
11351071
}
1136-
return OpcodesForSpill[OpcodeIndex];
1072+
return OpcodeIndex;
11371073
}
11381074

11391075
unsigned
1140-
PPCInstrInfo::getLoadOpcodeForSpill(unsigned Reg,
1141-
const TargetRegisterClass *RC) const {
1142-
const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1143-
int OpcodeIndex = 0;
1076+
PPCInstrInfo::getStoreOpcodeForSpill(const TargetRegisterClass *RC) const {
1077+
const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1078+
return OpcodesForSpill[getSpillIndex(RC)];
1079+
}
11441080

1145-
if (RC != nullptr) {
1146-
if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1147-
PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1148-
OpcodeIndex = SOK_Int4Spill;
1149-
} else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1150-
PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1151-
OpcodeIndex = SOK_Int8Spill;
1152-
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1153-
OpcodeIndex = SOK_Float8Spill;
1154-
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1155-
OpcodeIndex = SOK_Float4Spill;
1156-
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1157-
OpcodeIndex = SOK_SPESpill;
1158-
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1159-
OpcodeIndex = SOK_CRSpill;
1160-
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1161-
OpcodeIndex = SOK_CRBitSpill;
1162-
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1163-
OpcodeIndex = SOK_VRVectorSpill;
1164-
} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1165-
OpcodeIndex = SOK_VSXVectorSpill;
1166-
} else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1167-
OpcodeIndex = SOK_VectorFloat8Spill;
1168-
} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1169-
OpcodeIndex = SOK_VectorFloat4Spill;
1170-
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1171-
OpcodeIndex = SOK_VRSaveSpill;
1172-
} else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1173-
OpcodeIndex = SOK_QuadFloat8Spill;
1174-
} else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1175-
OpcodeIndex = SOK_QuadFloat4Spill;
1176-
} else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1177-
OpcodeIndex = SOK_QuadBitSpill;
1178-
} else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1179-
OpcodeIndex = SOK_SpillToVSR;
1180-
} else {
1181-
llvm_unreachable("Unknown regclass!");
1182-
}
1183-
} else {
1184-
if (PPC::GPRCRegClass.contains(Reg) ||
1185-
PPC::GPRC_NOR0RegClass.contains(Reg)) {
1186-
OpcodeIndex = SOK_Int4Spill;
1187-
} else if (PPC::G8RCRegClass.contains(Reg) ||
1188-
PPC::G8RC_NOX0RegClass.contains(Reg)) {
1189-
OpcodeIndex = SOK_Int8Spill;
1190-
} else if (PPC::F8RCRegClass.contains(Reg)) {
1191-
OpcodeIndex = SOK_Float8Spill;
1192-
} else if (PPC::F4RCRegClass.contains(Reg)) {
1193-
OpcodeIndex = SOK_Float4Spill;
1194-
} else if (PPC::SPERCRegClass.contains(Reg)) {
1195-
OpcodeIndex = SOK_SPESpill;
1196-
} else if (PPC::CRRCRegClass.contains(Reg)) {
1197-
OpcodeIndex = SOK_CRSpill;
1198-
} else if (PPC::CRBITRCRegClass.contains(Reg)) {
1199-
OpcodeIndex = SOK_CRBitSpill;
1200-
} else if (PPC::VRRCRegClass.contains(Reg)) {
1201-
OpcodeIndex = SOK_VRVectorSpill;
1202-
} else if (PPC::VSRCRegClass.contains(Reg)) {
1203-
OpcodeIndex = SOK_VSXVectorSpill;
1204-
} else if (PPC::VSFRCRegClass.contains(Reg)) {
1205-
OpcodeIndex = SOK_VectorFloat8Spill;
1206-
} else if (PPC::VSSRCRegClass.contains(Reg)) {
1207-
OpcodeIndex = SOK_VectorFloat4Spill;
1208-
} else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1209-
OpcodeIndex = SOK_VRSaveSpill;
1210-
} else if (PPC::QFRCRegClass.contains(Reg)) {
1211-
OpcodeIndex = SOK_QuadFloat8Spill;
1212-
} else if (PPC::QSRCRegClass.contains(Reg)) {
1213-
OpcodeIndex = SOK_QuadFloat4Spill;
1214-
} else if (PPC::QBRCRegClass.contains(Reg)) {
1215-
OpcodeIndex = SOK_QuadBitSpill;
1216-
} else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1217-
OpcodeIndex = SOK_SpillToVSR;
1218-
} else {
1219-
llvm_unreachable("Unknown regclass!");
1220-
}
1221-
}
1222-
return OpcodesForSpill[OpcodeIndex];
1081+
unsigned
1082+
PPCInstrInfo::getLoadOpcodeForSpill(const TargetRegisterClass *RC) const {
1083+
const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1084+
return OpcodesForSpill[getSpillIndex(RC)];
12231085
}
12241086

12251087
void PPCInstrInfo::StoreRegToStackSlot(
12261088
MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
12271089
const TargetRegisterClass *RC,
12281090
SmallVectorImpl<MachineInstr *> &NewMIs) const {
1229-
unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1091+
unsigned Opcode = getStoreOpcodeForSpill(RC);
12301092
DebugLoc DL;
12311093

12321094
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
@@ -1289,7 +1151,7 @@ void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
12891151
const TargetRegisterClass *RC,
12901152
SmallVectorImpl<MachineInstr *> &NewMIs)
12911153
const {
1292-
unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1154+
unsigned Opcode = getLoadOpcodeForSpill(RC);
12931155
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
12941156
FrameIdx));
12951157
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
@@ -2436,36 +2298,16 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI(
24362298
return OpNoForForwarding == ~0U ? nullptr : DefMI;
24372299
}
24382300

2301+
unsigned PPCInstrInfo::getSpillTarget() const {
2302+
return Subtarget.hasP9Vector() ? 1 : 0;
2303+
}
2304+
24392305
const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2440-
static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2441-
// Power 8
2442-
{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2443-
PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2444-
PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2445-
PPC::SPILLTOVSR_ST, PPC::EVSTDD},
2446-
// Power 9
2447-
{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2448-
PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2449-
PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2450-
PPC::SPILLTOVSR_ST}};
2451-
2452-
return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2306+
return StoreSpillOpcodesArray[getSpillTarget()];
24532307
}
24542308

24552309
const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2456-
static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2457-
// Power 8
2458-
{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2459-
PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2460-
PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2461-
PPC::SPILLTOVSR_LD, PPC::EVLDD},
2462-
// Power 9
2463-
{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2464-
PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2465-
PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2466-
PPC::SPILLTOVSR_LD}};
2467-
2468-
return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2310+
return LoadSpillOpcodesArray[getSpillTarget()];
24692311
}
24702312

24712313
void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,

0 commit comments

Comments
 (0)