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[SelectionDAG] Check use before combining into USUBSAT
Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D105789
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2 files changed

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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3209,7 +3209,7 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) {
32093209

32103210
// Try to find umax(a,b) - b or a - umin(a,b) patterns
32113211
// they may be converted to usubsat(a,b).
3212-
if (Op0.getOpcode() == ISD::UMAX) {
3212+
if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
32133213
SDValue MaxLHS = Op0.getOperand(0);
32143214
SDValue MaxRHS = Op0.getOperand(1);
32153215
if (MaxLHS == Op1)
@@ -3218,7 +3218,7 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) {
32183218
return getTruncatedUSUBSAT(DstVT, SubVT, MaxLHS, Op1, DAG, SDLoc(N));
32193219
}
32203220

3221-
if (Op1.getOpcode() == ISD::UMIN) {
3221+
if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) {
32223222
SDValue MinLHS = Op1.getOperand(0);
32233223
SDValue MinRHS = Op1.getOperand(1);
32243224
if (MinLHS == Op0)
@@ -3229,7 +3229,8 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) {
32293229

32303230
// sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit)))
32313231
if (Op1.getOpcode() == ISD::TRUNCATE &&
3232-
Op1.getOperand(0).getOpcode() == ISD::UMIN) {
3232+
Op1.getOperand(0).getOpcode() == ISD::UMIN &&
3233+
Op1.getOperand(0).hasOneUse()) {
32333234
SDValue MinLHS = Op1.getOperand(0).getOperand(0);
32343235
SDValue MinRHS = Op1.getOperand(0).getOperand(1);
32353236
if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0)

llvm/test/CodeGen/PowerPC/sat-add.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -864,3 +864,33 @@ define <4 x i128> @sadd(<4 x i128> %a, <4 x i128> %b) local_unnamed_addr {
864864
ret <4 x i128> %c
865865
}
866866

867+
define i64 @unsigned_sat_constant_i64_with_single_use(i64 %x) {
868+
; CHECK-LABEL: unsigned_sat_constant_i64_with_single_use:
869+
; CHECK: # %bb.0:
870+
; CHECK-NEXT: addi 4, 3, -4
871+
; CHECK-NEXT: cmpld 4, 3
872+
; CHECK-NEXT: iselgt 3, 0, 4
873+
; CHECK-NEXT: blr
874+
%umin = call i64 @llvm.umin.i64(i64 %x, i64 4)
875+
%sub = sub i64 %x, %umin
876+
ret i64 %sub
877+
}
878+
879+
define i64 @unsigned_sat_constant_i64_with_multiple_use(i64 %x, i64 %y) {
880+
; CHECK-LABEL: unsigned_sat_constant_i64_with_multiple_use:
881+
; CHECK: # %bb.0:
882+
; CHECK-NEXT: li 5, 4
883+
; CHECK-NEXT: cmpldi 3, 4
884+
; CHECK-NEXT: isellt 5, 3, 5
885+
; CHECK-NEXT: sub 3, 3, 5
886+
; CHECK-NEXT: add 4, 4, 5
887+
; CHECK-NEXT: mulld 3, 3, 4
888+
; CHECK-NEXT: blr
889+
%umin = call i64 @llvm.umin.i64(i64 %x, i64 4)
890+
%sub = sub i64 %x, %umin
891+
%add = add i64 %y, %umin
892+
%res = mul i64 %sub, %add
893+
ret i64 %res
894+
}
895+
896+
declare i64 @llvm.umin.i64(i64, i64)

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