[MipsISelLowering] avoid emitting libcalls to __multi3

Similar to D108842 and D108844.

__has_builtin(builtin_mul_overflow) returns true for 32b MIPS targets,
but Clang is deferring to compiler RT when encountering long long types.
This breaks MIPS malta_defconfig builds of the Linux kernel that are
using __builtin_mul_overflow with these types for these targets.

If the semantics of __has_builtin mean "the compiler resolves these,
always" then we shouldn't conditionally emit a libcall.

This will still need to be worked around in the Linux kernel in order to
continue to support malta_defconfig builds of the Linux kernel for this
target with older releases of clang.

Link: https://bugs.llvm.org/show_bug.cgi?id=28629
Link: ClangBuiltLinux/linux#1438

Reviewed By: rengolin

Differential Revision: https://reviews.llvm.org/D108926

Author: nickdesaulniers

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -509,6 +509,7 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
     setLibcallName(RTLIB::SHL_I128, nullptr);
     setLibcallName(RTLIB::SRL_I128, nullptr);
     setLibcallName(RTLIB::SRA_I128, nullptr);
+    setLibcallName(RTLIB::MUL_I128, nullptr);
     setLibcallName(RTLIB::MULO_I64, nullptr);
     setLibcallName(RTLIB::MULO_I128, nullptr);
   }

llvm/test/CodeGen/Mips/llvm-ir/mul.ll

@@ -230,7 +230,7 @@ define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: mul_i128:
 
-  ; GP32:           lw      $25, %call16(__multi3)($gp)
+  ; GP32-NOT:       lw      $25, %call16(__multi3)($gp)
 
   ; GP64-NOT-R6:    dmult   $4, $7
   ; GP64-NOT-R6:    mflo    $[[T0:[0-9]+]]
@@ -249,7 +249,7 @@ entry:
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
   ; 64R6-DAG:       dmul    $3, $5, $7
 
-  ; MM32:           lw      $25, %call16(__multi3)($16)
+  ; MM32-NOT:       lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
   ret i128 %r

llvm/test/CodeGen/Mips/overflow-intrinsic-optimizations.ll

@@ -3,6 +3,7 @@
 define i1 @no__mulodi4(i32 %a, i64 %b, i32* %c) {
 ; CHECK-LABEL: no__mulodi4
 ; CHECK-NOT: jal __mulodi4
+; CHECK-NOT: jal __multi3
 entry:
   %0 = sext i32 %a to i64
   %1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b)

llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll

@@ -148,43 +148,51 @@ define i1 @test_urem_negative_odd(i9 %X) nounwind {
 define i1 @test_urem_oversized(i66 %X) nounwind {
 ; MIPSEL-LABEL: test_urem_oversized:
 ; MIPSEL:       # %bb.0:
-; MIPSEL-NEXT:    addiu $sp, $sp, -40
-; MIPSEL-NEXT:    sw $ra, 36($sp) # 4-byte Folded Spill
-; MIPSEL-NEXT:    move $7, $6
-; MIPSEL-NEXT:    move $6, $5
-; MIPSEL-NEXT:    move $5, $4
 ; MIPSEL-NEXT:    lui $1, 12057
 ; MIPSEL-NEXT:    ori $1, $1, 37186
-; MIPSEL-NEXT:    lui $2, 52741
-; MIPSEL-NEXT:    ori $2, $2, 40665
-; MIPSEL-NEXT:    sw $2, 28($sp)
-; MIPSEL-NEXT:    sw $1, 24($sp)
-; MIPSEL-NEXT:    addiu $1, $zero, 2
-; MIPSEL-NEXT:    sw $1, 20($sp)
-; MIPSEL-NEXT:    sw $zero, 16($sp)
-; MIPSEL-NEXT:    jal __multi3
-; MIPSEL-NEXT:    addiu $4, $zero, 0
-; MIPSEL-NEXT:    sll $1, $4, 31
-; MIPSEL-NEXT:    srl $2, $5, 1
-; MIPSEL-NEXT:    or $1, $2, $1
-; MIPSEL-NEXT:    lui $2, 60010
-; MIPSEL-NEXT:    ori $2, $2, 61135
-; MIPSEL-NEXT:    sltu $1, $1, $2
-; MIPSEL-NEXT:    srl $2, $4, 1
-; MIPSEL-NEXT:    andi $3, $3, 3
-; MIPSEL-NEXT:    sll $4, $3, 31
-; MIPSEL-NEXT:    or $4, $2, $4
+; MIPSEL-NEXT:    multu $6, $1
+; MIPSEL-NEXT:    mflo $2
+; MIPSEL-NEXT:    mfhi $3
+; MIPSEL-NEXT:    lui $7, 52741
+; MIPSEL-NEXT:    ori $7, $7, 40665
+; MIPSEL-NEXT:    multu $6, $7
+; MIPSEL-NEXT:    mflo $8
+; MIPSEL-NEXT:    mfhi $9
+; MIPSEL-NEXT:    multu $5, $7
+; MIPSEL-NEXT:    mfhi $10
+; MIPSEL-NEXT:    mflo $11
+; MIPSEL-NEXT:    addu $9, $11, $9
+; MIPSEL-NEXT:    addu $12, $2, $9
+; MIPSEL-NEXT:    sltu $9, $9, $11
+; MIPSEL-NEXT:    sll $11, $12, 31
+; MIPSEL-NEXT:    sltu $2, $12, $2
+; MIPSEL-NEXT:    srl $13, $8, 1
+; MIPSEL-NEXT:    sll $8, $8, 1
+; MIPSEL-NEXT:    addu $2, $3, $2
+; MIPSEL-NEXT:    or $3, $13, $11
+; MIPSEL-NEXT:    srl $11, $12, 1
+; MIPSEL-NEXT:    addu $9, $10, $9
+; MIPSEL-NEXT:    mul $4, $4, $7
+; MIPSEL-NEXT:    mul $1, $5, $1
+; MIPSEL-NEXT:    sll $5, $6, 1
+; MIPSEL-NEXT:    lui $6, 60010
+; MIPSEL-NEXT:    ori $6, $6, 61135
+; MIPSEL-NEXT:    addu $2, $9, $2
+; MIPSEL-NEXT:    addu $1, $1, $2
+; MIPSEL-NEXT:    addu $2, $5, $4
+; MIPSEL-NEXT:    addu $1, $1, $2
+; MIPSEL-NEXT:    andi $1, $1, 3
+; MIPSEL-NEXT:    sll $2, $1, 31
+; MIPSEL-NEXT:    or $4, $11, $2
 ; MIPSEL-NEXT:    sltiu $2, $4, 13
 ; MIPSEL-NEXT:    xori $4, $4, 13
-; MIPSEL-NEXT:    movz $2, $1, $4
-; MIPSEL-NEXT:    sll $1, $5, 1
-; MIPSEL-NEXT:    srl $3, $3, 1
-; MIPSEL-NEXT:    or $1, $3, $1
+; MIPSEL-NEXT:    sltu $3, $3, $6
+; MIPSEL-NEXT:    movz $2, $3, $4
+; MIPSEL-NEXT:    srl $1, $1, 1
+; MIPSEL-NEXT:    or $1, $1, $8
 ; MIPSEL-NEXT:    andi $1, $1, 3
-; MIPSEL-NEXT:    movn $2, $zero, $1
-; MIPSEL-NEXT:    lw $ra, 36($sp) # 4-byte Folded Reload
 ; MIPSEL-NEXT:    jr $ra
-; MIPSEL-NEXT:    addiu $sp, $sp, 40
+; MIPSEL-NEXT:    movn $2, $zero, $1
 ;
 ; MIPS64EL-LABEL: test_urem_oversized:
 ; MIPS64EL:       # %bb.0: