Page Fault Vector Typo (#123)

* Page Fault Vector Typo

* Femtoseconds conversion

* RSDP Typo 

The signature for the RSDP is "RSD PTR ", and it is not an SDT. 

https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html?highlight=rsdt#root-system-description-table-rsdt

* APIC Address Incorrect

Fixed the description of the APIC address (the physaddr is not shifted, but the lower bits are masked), and fixed a typo with the location. On my ``qemu-system-x86_64``, the LAPIC base is 0xFEE00000 in physical memory.

* Latex-style exponent

* C struct syntax error

You need to create a entry in the symbol table to reference a C-object itself, e.g. for self-referencing in a struct

Author: KnudAndersen

02_Architecture/06_ACPITables.md

@@ -124,8 +124,8 @@ The RSDT is an SDT header followed by an array of `uint32_t`s, representing the
 The XSDT is the same, except the array is of `uint64_t`s.
 
 ```c
-struct RSDP {
-    ACPISDTHeader sdtHeader; //signature "RSDP"
+struct RSDT {
+    ACPISDTHeader sdtHeader; //signature "RSDT"
     uint32_t sdtAddresses[];
 };
 

02_Architecture/07_APIC.md

@@ -63,10 +63,10 @@ This register contains the following information:
 * Bit 8: if set, it means that the processor is the Bootstrap Processor (BSP).
 * Bits 9:10: reserved.
 * Bit 11: APIC global enable. This bit can be cleared to disable the local APIC for this processor. Realistically there is no reason to do this on modern processors.
-* Bits 12:31: Contains the base address of the local APIC for this processor core.
+* Bits 12:31: Contains the base address of the local APIC for this processor core. NOTE: The value read from these bits should not be shifted, e.g. if you read ``0xFEE00``, then the address is ``0xFEE00000``, just with bits 0:11 zeroed out.  
 * Bits 32:63: reserved.
 
-Note that the registers are given as a *physical address*, so to access these we will need to map them somewhere in the virtual address space. This is true for the addresses of any I/O APICs we obtain as well. When the system boots, the base address is usually `0xFEE0000` and often this is the value we read from `rdmsr`. For correct operation the local APIC registers should be mapped as 'strong uncachable'.
+Note that the registers are given as a *physical address*, so to access these we will need to map them somewhere in the virtual address space. This is true for the addresses of any I/O APICs we obtain as well. When the system boots, the base address is usually `0xFEE00000` and often this is the value we read from `rdmsr`. For correct operation the local APIC registers should be mapped as 'strong uncachable'.
 
 A complete list of local APIC registers is available in the Intel/AMD software development manuals, but the important ones for now are:
 

02_Architecture/08_Timers.md

@@ -143,7 +143,7 @@ Each register is accessed by adding an offset to the base address we obtained be
 - General configuration: offset `0x10`.
 - Main counter value: `0xF0`.
 
-We can read the main counter at any time, which is measured in timer ticks. We can convert these ticks into realtime by multiplying them with the timer period in the general capabilities register. Bits 63:32 of the general capabilities register contain the number of femtoseconds for each tick. A nanosecond is 1000 femtoseconds, and 1 second is 1'000'000'000 femtoseconds.
+We can read the main counter at any time, which is measured in timer ticks. We can convert these ticks into realtime by multiplying them with the timer period in the general capabilities register. Bits 63:32 of the general capabilities register contain the number of femtoseconds for each tick. A nanosecond is 1'000'000 femtoseconds, and 1 second is $10^{15}$ femtoseconds.
 
 We can also write to the main counter, usually we would write a 0 here when initializing the HPET in order to be able to determine uptime, but this is not really necessary.
 

04_Memory_Management/03_Paging.md

@@ -85,7 +85,7 @@ There are 3 possible scenarios:
 * 2Mib Pages: in this case we only need 3 page levels.
 * 1Gib Pages: Only 2 levels are needed.
 
-To implement paging, is strongly recommended to have already implemented interrupts too, specifically handling #PF (vector 0xd).
+To implement paging, is strongly recommended to have already implemented interrupts too, specifically handling #PF (vector 0xE).
 
 The 4 levels of page directories/tables are:
 

04_Memory_Management/04_Virtual_Memory_Manager.md

@@ -38,11 +38,11 @@ In addition, we might want to store some flags in the *vm object*, they are like
 Here's what our example virtual memory object looks like:
 
 ```c
-typedef struct {
+typedef struct vm_object {
     uintptr_t base;
     size_t length;
     size_t flags;
-    vm_object* next;
+    struct vm_object* next;
 } vm_object;
 
 #define VM_FLAG_NONE 0