feat: 更新属性处理，优化 reg 数据访问和增加新属性方法

Author: ZR233

fdt-edit/src/node/mod.rs

@@ -553,7 +553,6 @@ impl<'a> From<fdt_raw::Node<'a>> for Node {
             if prop.name() == "reg" {
                 if let Some(reg_iter) = raw_node.reg() {
                     let entries = reg_iter
-                        .iter()
                         .map(|e| super::prop::Reg {
                             address: e.address,
                             size: e.size,

fdt-edit/src/prop/mod.rs

@@ -265,7 +265,7 @@ impl<'a> From<fdt_raw::Property<'a>> for Property {
         if prop.name() == "reg" {
             return Property {
                 name,
-                kind: PropertyKind::Raw(RawProperty(prop.data().to_vec())),
+                kind: PropertyKind::Raw(RawProperty(prop.as_slice().to_vec())),
             };
         }
 
@@ -338,15 +338,15 @@ impl<'a> From<fdt_raw::Property<'a>> for Property {
                 } else {
                     Property {
                         name,
-                        kind: PropertyKind::Raw(RawProperty(prop.data().to_vec())),
+                        kind: PropertyKind::Raw(RawProperty(prop.as_slice().to_vec())),
                     }
                 }
             }
             _ => {
                 // 未知属性，使用原始数据
                 Property {
                     name,
-                    kind: PropertyKind::Raw(RawProperty(prop.data().to_vec())),
+                    kind: PropertyKind::Raw(RawProperty(prop.as_slice().to_vec())),
                 }
             }
         }

fdt-raw/src/data.rs

@@ -6,7 +6,7 @@ use core::{
 use crate::define::{FdtError, Token};
 
 #[derive(Clone)]
-pub(crate) struct Bytes<'a> {
+pub struct Bytes<'a> {
     pub(crate) all: &'a [u8],
     range: Range<usize>,
 }
@@ -80,7 +80,7 @@ impl<'a> Bytes<'a> {
 }
 
 #[derive(Clone)]
-pub(crate) struct Reader<'a> {
+pub struct Reader<'a> {
     pub(crate) bytes: Bytes<'a>,
     pub(crate) iter: usize,
 }

fdt-raw/src/node/prop/mod.rs

@@ -7,7 +7,7 @@ use core::fmt;
 
 use log::error;
 
-pub use reg::{RegInfo, RegIter};
+pub use reg::{Reg, RegInfo, RegIter};
 
 use super::NodeContext;
 use crate::{
@@ -53,6 +53,11 @@ impl<'a> Property<'a> {
         self.data.as_str_iter()
     }
 
+    /// 获取数据作为字节切片
+    pub fn as_slice(&self) -> &[u8] {
+        self.data.as_slice()
+    }
+
     /// 作为单个 u64 值
     pub fn as_u64(&self) -> Option<u64> {
         let mut iter = self.as_u32_iter();
@@ -130,6 +135,56 @@ impl<'a> Property<'a> {
             None
         }
     }
+
+    /// 获取为 device_type 字符串
+    pub fn as_device_type(&self) -> Option<&'a str> {
+        if self.name == "device_type" {
+            self.as_str()
+        } else {
+            None
+        }
+    }
+
+    /// 获取为 interrupt-parent
+    pub fn as_interrupt_parent(&self) -> Option<Phandle> {
+        if self.name == "interrupt-parent" {
+            self.as_u32().map(Phandle::from)
+        } else {
+            None
+        }
+    }
+
+    /// 获取为 clock-names 字符串列表
+    pub fn as_clock_names(&self) -> Option<StrIter<'a>> {
+        if self.name == "clock-names" {
+            Some(self.as_str_iter())
+        } else {
+            None
+        }
+    }
+
+    /// 获取为 compatible 字符串列表
+    pub fn as_compatible(&self) -> Option<StrIter<'a>> {
+        if self.name == "compatible" {
+            Some(self.as_str_iter())
+        } else {
+            None
+        }
+    }
+
+    /// 获取为 reg 属性（需要 context 信息）
+    pub fn as_reg(&self, address_cells: u32, size_cells: u32) -> Option<Reg<'a>> {
+        if self.name == "reg" {
+            Some(Reg::new(self.data.as_slice(), address_cells as u8, size_cells as u8))
+        } else {
+            None
+        }
+    }
+
+    /// 是否为 dma-coherent 属性
+    pub fn is_dma_coherent(&self) -> bool {
+        self.name == "dma-coherent" && self.data.is_empty()
+    }
 }
 
 impl fmt::Display for Property<'_> {
@@ -151,6 +206,34 @@ impl fmt::Display for Property<'_> {
             write!(f, "status = \"{:?}\"", s)
         } else if let Some(p) = self.as_phandle() {
             write!(f, "phandle = {}", p)
+        } else if let Some(p) = self.as_interrupt_parent() {
+            write!(f, "interrupt-parent = {}", p)
+        } else if let Some(s) = self.as_device_type() {
+            write!(f, "device_type = \"{}\"", s)
+        } else if let Some(iter) = self.as_compatible() {
+            write!(f, "compatible = ")?;
+            let mut first = true;
+            for s in iter.clone() {
+                if !first {
+                    write!(f, ", ")?;
+                }
+                write!(f, "\"{}\"", s)?;
+                first = false;
+            }
+            Ok(())
+        } else if let Some(iter) = self.as_clock_names() {
+            write!(f, "clock-names = ")?;
+            let mut first = true;
+            for s in iter.clone() {
+                if !first {
+                    write!(f, ", ")?;
+                }
+                write!(f, "\"{}\"", s)?;
+                first = false;
+            }
+            Ok(())
+        } else if self.is_dma_coherent() {
+            write!(f, "dma-coherent")
         } else if let Some(s) = self.as_str() {
             // 检查是否有多个字符串
             if self.data().iter().filter(|&&b| b == 0).count() > 1 {

fdt-raw/src/node/prop/reg.rs

@@ -1,6 +1,40 @@
 //! Reg 属性相关类型
 
-use crate::data::{Reader, U32Iter};
+use crate::data::{Bytes, Reader, U32Iter};
+
+/// Reg 属性包装器
+#[derive(Clone)]
+pub struct Reg<'a> {
+    data: &'a [u8],
+    address_cells: u8,
+    size_cells: u8,
+}
+
+impl<'a> Reg<'a> {
+    pub(crate) fn new(data: &'a [u8], address_cells: u8, size_cells: u8) -> Self {
+        Self {
+            data,
+            address_cells,
+            size_cells,
+        }
+    }
+
+    /// 获取 reg 数据的原始字节
+    pub fn as_slice(&self) -> &[u8] {
+        self.data
+    }
+
+    /// 获取 u32 迭代器
+    pub fn as_u32_iter(&self) -> U32Iter<'a> {
+        Bytes::new(self.data).as_u32_iter()
+    }
+
+    /// 获取 reg 信息迭代器
+    pub fn iter(&self) -> RegIter<'a> {
+        let bytes = Bytes::new(self.data);
+        RegIter::new(bytes.reader(), self.address_cells, self.size_cells)
+    }
+}
 
 /// Reg 条目信息
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]

fdt-raw/tests/node.rs

@@ -447,12 +447,12 @@ fn test_node_properties() {
     let mut found_address_cells = false;
     let mut found_size_cells = false;
     let mut found_interrupt_cells = false;
-    let found_device_type = false;
-    let found_compatible = false;
-    let found_phandle = false;
-    let found_interrupt_parent = false;
-    let found_reg = false;
-    let found_dma_coherent = false;
+    let mut found_device_type = false;
+    let mut found_compatible = false;
+    let mut found_phandle = false;
+    let mut found_interrupt_parent = false;
+    let mut found_reg = false;
+    let mut found_dma_coherent = false;
     let mut found_empty_property = false;
 
     for node in fdt.all_nodes() {
@@ -488,6 +488,27 @@ fn test_node_properties() {
                 match s {
                     Status::Okay | Status::Disabled => {}
                 }
+            } else if let Some(iter) = prop.as_compatible() {
+                let strs: Vec<_> = iter.clone().collect();
+                if !strs.is_empty() {
+                    found_compatible = true;
+                    info!("  compatible = {:?}", strs);
+                }
+            } else if let Some(s) = prop.as_device_type() {
+                found_device_type = true;
+                info!("  device_type = \"{}\"", s);
+            } else if prop.as_phandle().is_some() {
+                found_phandle = true;
+                info!("  {} = <{:?}>", prop.name(), prop.as_phandle());
+            } else if prop.as_interrupt_parent().is_some() {
+                found_interrupt_parent = true;
+                info!("  {} = <{:?}>", prop.name(), prop.as_interrupt_parent());
+            } else if prop.name() == "reg" {
+                found_reg = true;
+                info!("  reg ({} bytes)", prop.len());
+            } else if prop.name() == "dma-coherent" {
+                found_dma_coherent = true;
+                info!("  dma-coherent (empty)");
             } else {
                 // 处理未知属性
                 if let Some(s) = prop.as_str() {
@@ -743,8 +764,8 @@ fn test_memory_in_fdt(raw: &[u8], name: &str) {
                     );
                     info!("[{}]   device_type = \"{}\"", name, s);
                 } else if let Some(reg) = prop.as_reg(
-                    node.reg_address_cells() as u32,
-                    node.reg_size_cells() as u32,
+                    node.context.parent_address_cells.into(),
+                    node.context.parent_size_cells.into(),
                 ) {
                     found_reg = true;
                     let reg_infos: Vec<_> = reg.iter().collect();
@@ -754,8 +775,8 @@ fn test_memory_in_fdt(raw: &[u8], name: &str) {
                     info!(
                         "[{}]     address_cells={}, size_cells={}",
                         name,
-                        node.reg_address_cells(),
-                        node.reg_size_cells()
+                        node.context.parent_address_cells,
+                        node.context.parent_size_cells
                     );
                     info!(
                         "[{}]     raw data ({} bytes): {:02x?}",
@@ -823,7 +844,7 @@ fn test_memory_in_fdt(raw: &[u8], name: &str) {
 
                             // RPi 4B 的特殊情况 - 当前测试数据显示地址和大小为0
                             // 这可能是测试数据的特殊情况，我们只验证基本结构
-                            if node.reg_size_cells() == 1 {
+                            if node.context.parent_size_cells == 1 {
                                 assert_eq!(
                                     reg.as_slice().len() % 12,
                                     0,
@@ -841,7 +862,7 @@ fn test_memory_in_fdt(raw: &[u8], name: &str) {
 
                     // 验证 reg 数据长度的一致性
                     let expected_entry_size =
-                        (node.reg_address_cells() + node.reg_size_cells()) * 4;
+                        (node.context.parent_address_cells + node.context.parent_size_cells) * 4;
                     assert_eq!(
                         reg.as_slice().len() % expected_entry_size as usize,
                         0,