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1 file changed
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lines changedSubmodule llvm-project updated 35 files
- clang/lib/Sema/SemaTemplateDeductionGuide.cpp+4-1
- clang/unittests/AST/ASTImporterTest.cpp+23
- lld/MachO/BPSectionOrderer.cpp+11-21
- lld/include/lld/Common/BPSectionOrdererBase.inc+8-8
- llvm/lib/Analysis/LazyValueInfo.cpp+26
- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp+1-1
- llvm/lib/Target/AArch64/AArch64InstrInfo.td+3-3
- llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp+30-1
- llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp+32-3
- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp+34
- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h+3
- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp+52
- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp+13
- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h+5
- llvm/lib/Target/Xtensa/Xtensa.td+3-4
- llvm/lib/Target/Xtensa/XtensaFeatures.td+14
- llvm/lib/Target/Xtensa/XtensaInstrInfo.td+101
- llvm/lib/Target/Xtensa/XtensaOperands.td+21
- llvm/lib/Target/Xtensa/XtensaRegisterInfo.td+5-1
- llvm/lib/Target/Xtensa/XtensaSubtarget.h+6-1
- llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir+13-13
- llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir+12-12
- llvm/test/CodeGen/AArch64/fsh.ll+92-156
- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir+35-35
- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir+53-53
- llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv32.mir+6-6
- llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir+8-8
- llvm/test/MC/Disassembler/Xtensa/windowed.txt+71
- llvm/test/MC/Disassembler/Xtensa/windowed_code_density.txt+11
- llvm/test/MC/Xtensa/windowed.s+105
- llvm/test/MC/Xtensa/windowed_code_density.s+14
- llvm/test/MC/Xtensa/windowed_invalid.s+35
- llvm/test/Transforms/CorrelatedValuePropagation/cond-at-use.ll+4-6
- llvm/test/Transforms/CorrelatedValuePropagation/icmp.ll+12-24
- llvm/utils/update_mir_test_checks.py+1-1
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