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lines changedSubmodule llvm-project updated 90 files
- clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp+5-3
- clang-tools-extra/docs/ReleaseNotes.rst+7-3
- clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp+14
- clang/docs/SafeBuffers.rst+1-1
- clang/test/Driver/riscv-profiles.c+8
- clang/utils/TableGen/NeonEmitter.cpp+3-3
- compiler-rt/lib/ctx_profile/CtxInstrContextNode.h+3-3
- libcxx/include/CMakeLists.txt+1-3
- libcxx/include/__type_traits/add_const.h-32
- libcxx/include/__type_traits/add_cv_quals.h+20
- libcxx/include/__type_traits/add_volatile.h-32
- libcxx/include/__type_traits/is_trivially_assignable.h-1
- libcxx/include/__utility/as_const.h+1-4
- libcxx/include/any+1-1
- libcxx/include/module.modulemap+1-3
- libcxx/include/type_traits+1-3
- libcxx/include/variant+1-3
- lld/ELF/Driver.cpp+6-2
- lld/test/ELF/aarch64-feature-pac.s+7-5
- lld/test/ELF/aarch64-feature-pauth.s+55-3
- lldb/include/lldb/Interpreter/CommandObject.h+6-4
- lldb/source/Commands/CommandObjectMultiword.cpp+2-2
- llvm/docs/LangRef.rst+4-4
- llvm/docs/NVPTXUsage.rst+64
- llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h+7
- llvm/include/llvm/ExecutionEngine/Orc/Core.h+2-95
- llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h+47
- llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h+103
- llvm/include/llvm/IR/IntrinsicsNVVM.td+24
- llvm/include/llvm/ProfileData/CtxInstrContextNode.h+3-3
- llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp+3-3
- llvm/lib/CodeGen/GlobalISel/Utils.cpp+2-2
- llvm/lib/IR/DIBuilder.cpp+2-2
- llvm/lib/IR/DebugInfo.cpp+3-3
- llvm/lib/IR/Metadata.cpp+5-5
- llvm/lib/SandboxIR/Tracker.cpp+6-6
- llvm/lib/Target/AArch64/AArch64Features.td+2-5
- llvm/lib/Target/AArch64/AArch64Subtarget.cpp+12
- llvm/lib/Target/AArch64/AArch64Subtarget.h+4
- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp-1
- llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp-2
- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp+6-7
- llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp-2
- llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp-2
- llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp+1-4
- llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp-1
- llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp-1
- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp+7-7
- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp+2-2
- llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp+1-1
- llvm/lib/Target/BPF/BTFDebug.cpp+1-1
- llvm/lib/Target/M68k/M68kFrameLowering.cpp+4-2
- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp+90-14
- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h+1
- llvm/lib/Target/NVPTX/NVPTXIntrinsics.td+46
- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp+2-2
- llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp+41-46
- llvm/lib/Target/RISCV/RISCVProfiles.td+3-9
- llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp+2-2
- llvm/lib/Target/X86/X86ISelLowering.cpp-2
- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td-3
- llvm/lib/Target/X86/X86InstrInfo.cpp+1
- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp-2
- llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp+3-1
- llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp+2-2
- llvm/lib/Transforms/Scalar/SROA.cpp+3-5
- llvm/lib/Transforms/Utils/Local.cpp+2-2
- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp+2-1
- llvm/lib/Transforms/Vectorize/VPlan.cpp+1-1
- llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp+4-4
- llvm/test/CodeGen/AArch64/arm64-ext.ll+101-73
- llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll+1-1
- llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll+3-1
- llvm/test/CodeGen/AArch64/sve-vl-arith.ll+2-1
- llvm/test/CodeGen/M68k/multiple-return.ll+72-2
- llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll+144
- llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir+867
- llvm/test/CodeGen/RISCV/attributes.ll+7-7
- llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll+7-7
- llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect@create/sectcreate-data.txt
- llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test+1-1
- llvm/test/Transforms/InstCombine/vec_shuffle.ll+12
- llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll+2-12
- llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll+40
- llvm/tools/llvm-jitlink/llvm-jitlink.cpp+1-1
- llvm/utils/gn/secondary/libcxx/include/BUILD.gn+1-3
- mlir/include/mlir/IR/Dominance.h+10-5
- mlir/lib/IR/Dominance.cpp+6-4
- mlir/test/Analysis/test-dominance.mlir+585-210
- mlir/test/lib/IR/TestDominance.cpp+44-19
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