-
Notifications
You must be signed in to change notification settings - Fork 9
pre-commit: PR143745 #2425
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
pre-commit: PR143745 #2425
Conversation
Diff moderunner: ariselab-64c-docker 244 files changed, 470528 insertions(+), 474992 deletions(-) 6 18 bench/actix-rs/optimized/2o6s6qtmif526itx.ll |
|
Here is a brief summary of up to 5 major changes in the provided LLVM IR diff:
High-Level OverviewThe overall change appears to be a result of optimization passes removing unnecessary stack allocations introduced by SROA (Scalar Replacement of Aggregates), replacing them with more direct memory operations. This leads to:
These optimizations reduce stack usage and improve runtime efficiency by minimizing redundant memory operations. model: qwen-plus-latest |
| %.sroa.5.sroa.6.0..sroa.6.0..8.val.sroa_idx.i.sroa_idx.i = getelementptr inbounds nuw i8, ptr %.val, i64 24 | ||
| call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %.sroa.5.sroa.6.0..sroa.6.0..8.val.sroa_idx.i.sroa_idx.i, ptr noundef nonnull align 8 dereferenceable(16) %.sroa.532.i.i, i64 16, i1 false) | ||
| %.sroa.7.0..8.val.sroa_idx.i.i = getelementptr inbounds nuw i8, ptr %.val, i64 40 | ||
| call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %.sroa.7.0..8.val.sroa_idx.i.i, ptr noundef nonnull align 8 dereferenceable(32) %.sroa.10.i, i64 32, i1 false), !noalias !12593 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Regression.
|
/add-label regression reviewed |
|
/add-label regression |
Link: llvm/llvm-project#143745
Requested by: @nikic