diff --git a/bench/postgres/optimized/rewriteheap.ll b/bench/postgres/optimized/rewriteheap.ll index 7a27628c1e8..847e289213a 100644 --- a/bench/postgres/optimized/rewriteheap.ll +++ b/bench/postgres/optimized/rewriteheap.ll @@ -1071,14 +1071,14 @@ define dso_local void @CheckPointLogicalRewriteHeap() local_unnamed_addr #0 { call void @llvm.lifetime.start.p0(i64 1044, ptr nonnull %1) #13 %8 = tail call i64 @GetRedoRecPtr() #13 %9 = tail call i64 @ReplicationSlotsComputeLogicalRestartLSN() #13 - %.not = icmp ne i64 %9, 0 %10 = tail call ptr @AllocateDir(ptr noundef nonnull @.str.4) #13 %11 = tail call ptr @ReadDir(ptr noundef %10, ptr noundef nonnull @.str.4) #13 %.not2740 = icmp eq ptr %11, null br i1 %.not2740, label %._crit_edge, label %sub_0.lr.ph sub_0.lr.ph: ; preds = %0 - %spec.select = tail call i64 @llvm.umin.i64(i64 %8, i64 %9) + %.fr = freeze i64 %8 + %spec.select = tail call i64 @llvm.umin.i64(i64 %.fr, i64 %9) %12 = add i64 %spec.select, -1 br label %sub_0 @@ -1145,7 +1145,6 @@ sub_135: ; preds = %.tail %39 = zext i32 %38 to i64 %40 = or disjoint i64 %37, %39 %or.cond3.not32 = icmp ult i64 %12, %40 - %or.cond3.not = select i1 %.not, i1 %or.cond3.not32, i1 false br i1 %or.cond3.not, label %52, label %41 41: ; preds = %34 diff --git a/bench/recastnavigation/optimized/catch_amalgamated.ll b/bench/recastnavigation/optimized/catch_amalgamated.ll index 7828338c980..99216e1dfe5 100644 --- a/bench/recastnavigation/optimized/catch_amalgamated.ll +++ b/bench/recastnavigation/optimized/catch_amalgamated.ll @@ -38927,7 +38927,7 @@ define dso_local void @_ZN5Catch17parseReporterSpecENS_9StringRefE(ptr dead_on_u %35 = getelementptr inbounds %"class.std::__cxx11::basic_string", ptr %34, i64 %.013108 %36 = call noundef ptr @_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5c_strEv(ptr noundef nonnull align 8 dereferenceable(32) %35) #56 %37 = call noundef i64 @_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(32) %35) #56 - %38 = getelementptr inbounds i8, ptr %36, i64 %37 + %38 = getelementptr i8, ptr %36, i64 %37 %39 = ptrtoint ptr %38 to i64 %40 = ptrtoint ptr %36 to i64 %41 = ashr i64 %37, 2 @@ -39031,7 +39031,6 @@ define dso_local void @_ZN5Catch17parseReporterSpecENS_9StringRefE(ptr dead_on_u %.not.i = icmp eq i64 %37, 0 %81 = call i64 @llvm.umin.i64(i64 %37, i64 %80) %.sroa.0.0.i.i = select i1 %.not.i, ptr @.str.14, ptr %36 - %.sroa.4.0.i.i = select i1 %.not.i, i64 0, i64 %81 %82 = add i64 %80, 1 %83 = icmp ult i64 %82, %37 %84 = sub nuw i64 %37, %82 @@ -39039,7 +39038,7 @@ define dso_local void @_ZN5Catch17parseReporterSpecENS_9StringRefE(ptr dead_on_u %86 = call i64 @llvm.umin.i64(i64 %84, i64 %37) %.sroa.0.0.i2.i = select i1 %83, ptr %85, ptr @.str.14 %.sroa.4.0.i3.i = select i1 %83, i64 %86, i64 0 - %87 = icmp eq i64 %.sroa.4.0.i.i, 0 + %87 = icmp eq i64 %81, 0 %88 = icmp eq i64 %.sroa.4.0.i3.i, 0 %or.cond = select i1 %87, i1 true, i1 %88 br i1 %or.cond, label %89, label %90 @@ -39054,7 +39053,7 @@ define dso_local void @_ZN5Catch17parseReporterSpecENS_9StringRefE(ptr dead_on_u br i1 %92, label %93, label %121 93: ; preds = %90 - %94 = icmp eq i64 %.sroa.4.0.i.i, 1 + %94 = icmp eq i64 %81, 1 br i1 %94, label %95, label %96 95: ; preds = %93 @@ -39064,7 +39063,7 @@ define dso_local void @_ZN5Catch17parseReporterSpecENS_9StringRefE(ptr dead_on_u 96: ; preds = %93 call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) call void @_ZNSaIcEC1Ev(ptr noundef nonnull align 1 dereferenceable(1) %6) #56, !noalias !547 - invoke void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcmRKS3_(ptr noundef nonnull align 8 dereferenceable(32) %11, ptr noundef nonnull %.sroa.0.0.i.i, i64 noundef %.sroa.4.0.i.i, ptr noundef nonnull align 1 dereferenceable(1) %6) + invoke void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcmRKS3_(ptr noundef nonnull align 8 dereferenceable(32) %11, ptr noundef nonnull %.sroa.0.0.i.i, i64 noundef %81, ptr noundef nonnull align 1 dereferenceable(1) %6) to label %99 unwind label %97 97: ; preds = %96 @@ -39166,7 +39165,7 @@ _ZNKSt4lessINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEclERKS5_S8_.exi br label %.body 121: ; preds = %90 - switch i64 %.sroa.4.0.i.i, label %_ZNK5Catch9StringRefeqES0_.exit28.thread [ + switch i64 %81, label %_ZNK5Catch9StringRefeqES0_.exit28.thread [ i64 3, label %_ZNK5Catch9StringRefeqES0_.exit i64 11, label %_ZNK5Catch9StringRefeqES0_.exit28 ] diff --git a/bench/yosys/optimized/stat.ll b/bench/yosys/optimized/stat.ll index e101b699d74..adffccb3629 100644 --- a/bench/yosys/optimized/stat.ll +++ b/bench/yosys/optimized/stat.ll @@ -18316,25 +18316,26 @@ _ZN5Yosys5RTLIL8IdStringD2Ev.exit55: ; preds = %208, %214, %221 %.sroa.speculated70 = call i32 @llvm.umin.i32(i32 %238, i32 %101) %239 = sub i32 %101, %.sroa.speculated70 %240 = sub i32 %238, %.sroa.speculated70 + %241 = freeze i32 %240 br label %.thread .thread: ; preds = %_ZN5Yosys5RTLIL8IdStringD2Ev.exit55, %237 %.0129 = phi i32 [ %239, %237 ], [ %101, %_ZN5Yosys5RTLIL8IdStringD2Ev.exit55 ] - %.1 = phi i32 [ %240, %237 ], [ 0, %_ZN5Yosys5RTLIL8IdStringD2Ev.exit55 ] + %.1 = phi i32 [ %241, %237 ], [ 0, %_ZN5Yosys5RTLIL8IdStringD2Ev.exit55 ] + %.fr = freeze i32 %137 %.not32 = icmp eq i32 %173, 0 %241 = call i32 @llvm.usub.sat.i32(i32 %173, i32 %.0129) %.0130 = select i1 %.not32, i32 0, i32 %241 - %.not33 = icmp eq i32 %.1, 0 - %.sroa.speculated = call i32 @llvm.umin.i32(i32 %.1, i32 %137) - %242 = select i1 %.not33, i32 0, i32 %.sroa.speculated - %.0132 = sub i32 %137, %242 + %.sroa.speculated = call i32 @llvm.umin.i32(i32 %.1, i32 %.fr) + %.0132 = sub i32 %.fr, %.sroa.speculated %.not34 = icmp eq i32 %.0130, 0 %243 = call i32 @llvm.usub.sat.i32(i32 %.0130, i32 %.0132) %.1131 = select i1 %.not34, i32 0, i32 %243 + %.not33 = icmp eq i32 %.1, 0 %244 = sub i32 %.1, %.sroa.speculated %245 = add i32 %65, %29 %246 = add i32 %245, %101 - %247 = add i32 %246, %137 + %247 = add i32 %246, %.fr %248 = add i32 %244, 1 %249 = select i1 %.not33, i32 1, i32 %248 %250 = add i32 %249, %.1131 diff --git a/bench/zed-rs/optimized/eiu35781qwj0wy44b83i3e7bt.ll b/bench/zed-rs/optimized/eiu35781qwj0wy44b83i3e7bt.ll index 1091b17ef73..a7c018afb91 100644 --- a/bench/zed-rs/optimized/eiu35781qwj0wy44b83i3e7bt.ll +++ b/bench/zed-rs/optimized/eiu35781qwj0wy44b83i3e7bt.ll @@ -22281,7 +22281,7 @@ common.ret: ; preds = %210, %"_ZN50_$LT$T$ "_ZN50_$LT$T$u20$as$u20$core..convert..Into$LT$U$GT$$GT$4into17ha04ee329d7e6fdcfE.exit": ; preds = %"_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h10404877c56d9194E.exit", %"_ZN63_$LT$alloc..alloc..Global$u20$as$u20$core..alloc..Allocator$GT$10deallocate17hb66d9ce94201aa99E.llvm.10833762189268282141.exit.i.i1.i46", %45, %49, %54, %"_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit" %.sroa.082.0 = phi i64 [ %.sroa.017.i.sroa.0.0, %"_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit" ], [ -9223372036854775808, %54 ], [ -9223372036854775808, %49 ], [ -9223372036854775808, %45 ], [ -9223372036854775808, %"_ZN63_$LT$alloc..alloc..Global$u20$as$u20$core..alloc..Allocator$GT$10deallocate17hb66d9ce94201aa99E.llvm.10833762189268282141.exit.i.i1.i46" ], [ -9223372036854775808, %"_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h10404877c56d9194E.exit" ] %.sroa.683.0 = phi ptr [ %.sroa.017.i.sroa.5.0, %"_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit" ], [ %55, %54 ], [ %50, %49 ], [ %46, %45 ], [ %215, %"_ZN63_$LT$alloc..alloc..Global$u20$as$u20$core..alloc..Allocator$GT$10deallocate17hb66d9ce94201aa99E.llvm.10833762189268282141.exit.i.i1.i46" ], [ %215, %"_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h10404877c56d9194E.exit" ] - %.sroa.1184.0 = phi i64 [ %spec.select, %"_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit" ], [ undef, %54 ], [ undef, %49 ], [ undef, %45 ], [ undef, %"_ZN63_$LT$alloc..alloc..Global$u20$as$u20$core..alloc..Allocator$GT$10deallocate17hb66d9ce94201aa99E.llvm.10833762189268282141.exit.i.i1.i46" ], [ undef, %"_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h10404877c56d9194E.exit" ] + %.sroa.1184.0 = phi i64 [ %217, %"_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit" ], [ undef, %54 ], [ undef, %49 ], [ undef, %45 ], [ undef, %"_ZN63_$LT$alloc..alloc..Global$u20$as$u20$core..alloc..Allocator$GT$10deallocate17hb66d9ce94201aa99E.llvm.10833762189268282141.exit.i.i1.i46" ], [ undef, %"_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h10404877c56d9194E.exit" ] %.sroa.12.0 = phi i8 [ %218, %"_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit" ], [ undef, %54 ], [ undef, %49 ], [ undef, %45 ], [ undef, %"_ZN63_$LT$alloc..alloc..Global$u20$as$u20$core..alloc..Allocator$GT$10deallocate17hb66d9ce94201aa99E.llvm.10833762189268282141.exit.i.i1.i46" ], [ undef, %"_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h10404877c56d9194E.exit" ] store i64 %.sroa.082.0, ptr %0, align 8 %.sroa.683.0..sroa_idx = getelementptr inbounds nuw i8, ptr %0, i64 8 @@ -22882,8 +22882,8 @@ common.ret: ; preds = %210, %"_ZN50_$LT$T$ "_ZN5alloc3vec16Vec$LT$T$C$A$GT$8truncate17h55200e0956499113E.exit": ; preds = %.thread118 %216 = icmp eq i64 %.sroa.4.0.i, 0 - %217 = call i64 @llvm.umin.i64(i64 %.sroa.4.0.i, i64 %.sroa.017.i.sroa.6.0) - %spec.select = select i1 %216, i64 0, i64 %217 + %.sroa.017.i.sroa.6.0.fr = freeze i64 %.sroa.017.i.sroa.6.0 + %217 = call i64 @llvm.umin.i64(i64 %.sroa.4.0.i, i64 %.sroa.017.i.sroa.6.0.fr) %218 = zext i1 %216 to i8 br label %"_ZN50_$LT$T$u20$as$u20$core..convert..Into$LT$U$GT$$GT$4into17ha04ee329d7e6fdcfE.exit" diff --git a/scripts/setup_pre_commit_patch.sh b/scripts/setup_pre_commit_patch.sh index c5409e09ef4..2755994a456 100755 --- a/scripts/setup_pre_commit_patch.sh +++ b/scripts/setup_pre_commit_patch.sh @@ -2,7 +2,7 @@ set -euo pipefail shopt -s inherit_errexit -export GITHUB_PATCH_ID="/llvm-project/commit/" +export GITHUB_PATCH_ID=llvm/llvm-project/pull/147605 export COMPTIME_MODE=0 # Please rebase manually