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Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (llvm#116202)" chain
This reverts commit b36fcf4. This reverts commit c11b6b1. This reverts commit 775148f. multiple bot build breakages, e.g. https://lab.llvm.org/buildbot/#/builders/3/builds/8076
1 parent a9731df commit d1dae1e

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11 files changed

+20
-172
lines changed

11 files changed

+20
-172
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -512,10 +512,3 @@ bool RISCVTargetInfo::validateGlobalRegisterVariable(
512512
}
513513
return false;
514514
}
515-
516-
bool RISCVTargetInfo::validateCpuIs(StringRef CPUName) const {
517-
assert(getTriple().isOSLinux() &&
518-
"__builtin_cpu_is() is only supported for Linux.");
519-
520-
return llvm::RISCV::hasValidCPUModel(CPUName);
521-
}

‎clang/lib/Basic/Targets/RISCV.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,10 +128,8 @@ class RISCVTargetInfo : public TargetInfo {
128128
}
129129

130130
bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
131-
bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
132131
bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
133132
bool validateCpuSupports(StringRef Feature) const override;
134-
bool validateCpuIs(StringRef CPUName) const override;
135133
bool isValidFeatureName(StringRef Name) const override;
136134

137135
bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 0 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,6 @@
6666
#include "llvm/Support/ScopedPrinter.h"
6767
#include "llvm/TargetParser/AArch64TargetParser.h"
6868
#include "llvm/TargetParser/RISCVISAInfo.h"
69-
#include "llvm/TargetParser/RISCVTargetParser.h"
7069
#include "llvm/TargetParser/X86TargetParser.h"
7170
#include <optional>
7271
#include <utility>
@@ -22694,47 +22693,6 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
2269422693
return nullptr;
2269522694
}
2269622695

22697-
Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) {
22698-
const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
22699-
StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
22700-
return EmitRISCVCpuIs(CPUStr);
22701-
}
22702-
22703-
Value *CodeGenFunction::EmitRISCVCpuIs(StringRef CPUStr) {
22704-
llvm::Type *Int32Ty = Builder.getInt32Ty();
22705-
llvm::Type *Int64Ty = Builder.getInt64Ty();
22706-
llvm::StructType *StructTy = llvm::StructType::get(Int32Ty, Int64Ty, Int64Ty);
22707-
llvm::Constant *RISCVCPUModel =
22708-
CGM.CreateRuntimeVariable(StructTy, "__riscv_cpu_model");
22709-
cast<llvm::GlobalValue>(RISCVCPUModel)->setDSOLocal(true);
22710-
22711-
auto loadRISCVCPUID = [&](unsigned Index) {
22712-
Value *Ptr = Builder.CreateStructGEP(StructTy, RISCVCPUModel, Index);
22713-
Value *CPUID = Builder.CreateAlignedLoad(StructTy->getTypeAtIndex(Index),
22714-
Ptr, llvm::MaybeAlign());
22715-
return CPUID;
22716-
};
22717-
22718-
const llvm::RISCV::CPUModel Model = llvm::RISCV::getCPUModel(CPUStr);
22719-
22720-
// Compare mvendorid.
22721-
Value *VendorID = loadRISCVCPUID(0);
22722-
Value *Result =
22723-
Builder.CreateICmpEQ(VendorID, Builder.getInt32(Model.MVendorID));
22724-
22725-
// Compare marchid.
22726-
Value *ArchID = loadRISCVCPUID(1);
22727-
Result = Builder.CreateAnd(
22728-
Result, Builder.CreateICmpEQ(ArchID, Builder.getInt64(Model.MArchID)));
22729-
22730-
// Compare mimpid.
22731-
Value *ImpID = loadRISCVCPUID(2);
22732-
Result = Builder.CreateAnd(
22733-
Result, Builder.CreateICmpEQ(ImpID, Builder.getInt64(Model.MImpID)));
22734-
22735-
return Result;
22736-
}
22737-
2273822696
Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2273922697
const CallExpr *E,
2274022698
ReturnValueSlot ReturnValue) {
@@ -22743,8 +22701,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2274322701
return EmitRISCVCpuSupports(E);
2274422702
if (BuiltinID == Builtin::BI__builtin_cpu_init)
2274522703
return EmitRISCVCpuInit();
22746-
if (BuiltinID == Builtin::BI__builtin_cpu_is)
22747-
return EmitRISCVCpuIs(E);
2274822704

2274922705
SmallVector<Value *, 4> Ops;
2275022706
llvm::Type *ResultType = ConvertType(E->getType());

‎clang/lib/CodeGen/CodeGenFunction.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4730,8 +4730,6 @@ class CodeGenFunction : public CodeGenTypeCache {
47304730
llvm::Value *EmitRISCVCpuSupports(const CallExpr *E);
47314731
llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs);
47324732
llvm::Value *EmitRISCVCpuInit();
4733-
llvm::Value *EmitRISCVCpuIs(const CallExpr *E);
4734-
llvm::Value *EmitRISCVCpuIs(StringRef CPUStr);
47354733

47364734
void AddAMDGPUFenceAddressSpaceMMRA(llvm::Instruction *Inst,
47374735
const CallExpr *E);

‎clang/test/CodeGen/RISCV/builtin-cpu-is-error.c‎

Lines changed: 0 additions & 7 deletions
This file was deleted.

‎clang/test/CodeGen/RISCV/builtin-cpu-is.c‎

Lines changed: 0 additions & 39 deletions
This file was deleted.

‎llvm/include/llvm/TargetParser/RISCVTargetParser.h‎

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -32,21 +32,6 @@ struct RISCVExtensionBitmask {
3232
};
3333
} // namespace RISCVExtensionBitmaskTable
3434

35-
struct CPUModel {
36-
uint32_t MVendorID;
37-
uint64_t MArchID;
38-
uint64_t MImpID;
39-
};
40-
41-
struct CPUInfo {
42-
StringLiteral Name;
43-
StringLiteral DefaultMarch;
44-
bool FastScalarUnalignedAccess;
45-
bool FastVectorUnalignedAccess;
46-
CPUModel Model;
47-
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
48-
};
49-
5035
// We use 64 bits as the known part in the scalable vector types.
5136
static constexpr unsigned RVVBitsPerBlock = 64;
5237

@@ -60,8 +45,6 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
6045
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
6146
bool hasFastScalarUnalignedAccess(StringRef CPU);
6247
bool hasFastVectorUnalignedAccess(StringRef CPU);
63-
bool hasValidCPUModel(StringRef CPU);
64-
CPUModel getCPUModel(StringRef CPU);
6548

6649
} // namespace RISCV
6750

‎llvm/lib/Target/RISCV/RISCVProcessors.td‎

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -49,9 +49,6 @@ class RISCVProcessorModel<string n,
4949
string default_march = "">
5050
: ProcessorModel<n, m, f, tunef> {
5151
string DefaultMarch = default_march;
52-
int MVendorID = 0;
53-
int MArchID = 0;
54-
int MImpID = 0;
5552
}
5653

5754
class RISCVTuneProcessorModel<string n,
@@ -460,11 +457,7 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
460457
TuneZExtHFusion,
461458
TuneZExtWFusion,
462459
TuneShiftedZExtWFusion,
463-
TuneLDADDFusion]> {
464-
let MVendorID = 0x61f;
465-
let MArchID = 0x8000000000010000;
466-
let MImpID = 0x111;
467-
}
460+
TuneLDADDFusion]>;
468461

469462
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
470463
XiangShanNanHuModel,
@@ -510,11 +503,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
510503
[TuneDLenFactor2,
511504
TuneOptimizedNF2SegmentLoadStore,
512505
TuneOptimizedNF3SegmentLoadStore,
513-
TuneOptimizedNF4SegmentLoadStore]> {
514-
let MVendorID = 0x710;
515-
let MArchID = 0x8000000058000001;
516-
let MImpID = 0x1000000049772200;
517-
}
506+
TuneOptimizedNF4SegmentLoadStore]>;
518507

519508
def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
520509
NoSchedModel,

‎llvm/lib/TargetParser/RISCVTargetParser.cpp‎

Lines changed: 11 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -21,22 +21,24 @@ namespace RISCV {
2121

2222
enum CPUKind : unsigned {
2323
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
24-
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
24+
FAST_VECTOR_UNALIGN) \
2525
CK_##ENUM,
2626
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
2727
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
2828
};
2929

30+
struct CPUInfo {
31+
StringLiteral Name;
32+
StringLiteral DefaultMarch;
33+
bool FastScalarUnalignedAccess;
34+
bool FastVectorUnalignedAccess;
35+
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
36+
};
37+
3038
constexpr CPUInfo RISCVCPUInfo[] = {
3139
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
32-
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
33-
{ \
34-
NAME, \
35-
DEFAULT_MARCH, \
36-
FAST_SCALAR_UNALIGN, \
37-
FAST_VECTOR_UNALIGN, \
38-
{MVENDORID, MARCHID, MIMPID}, \
39-
},
40+
FAST_VECTOR_UNALIGN) \
41+
{NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
4042
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
4143
};
4244

@@ -57,18 +59,6 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
5759
return Info && Info->FastVectorUnalignedAccess;
5860
}
5961

60-
bool hasValidCPUModel(StringRef CPU) {
61-
const CPUModel Model = getCPUModel(CPU);
62-
return Model.MVendorID != 0 && Model.MArchID != 0 && Model.MImpID != 0;
63-
}
64-
65-
CPUModel getCPUModel(StringRef CPU) {
66-
const CPUInfo *Info = getCPUInfoByName(CPU);
67-
if (!Info)
68-
return {0, 0, 0};
69-
return Info->Model;
70-
}
71-
7262
bool parseCPU(StringRef CPU, bool IsRV64) {
7363
const CPUInfo *Info = getCPUInfoByName(CPU);
7464

‎llvm/test/TableGen/riscv-target-def.td‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -81,9 +81,6 @@ class RISCVProcessorModel<string n,
8181
string default_march = "">
8282
: ProcessorModel<n, m, f, tunef> {
8383
string DefaultMarch = default_march;
84-
int MVendorID = 0;
85-
int MArchID = 0;
86-
int MImpID = 0;
8784
}
8885

8986
class RISCVTuneProcessorModel<string n,
@@ -163,13 +160,13 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
163160
// CHECK: #endif // GET_SUPPORTED_PROFILES
164161

165162
// CHECK: #ifndef PROC
166-
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
163+
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
167164
// CHECK-NEXT: #endif
168165

169-
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
170-
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
171-
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
172-
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
166+
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
167+
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
168+
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
169+
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
173170

174171
// CHECK: #undef PROC
175172

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