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[NFC] llvm#155740 post cleanup (llvm#155966)
Remove all "approx-func-fp-math" in tests.
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17 files changed

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‎llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll‎

Lines changed: 1 addition & 118 deletions
Original file line numberDiff line numberDiff line change
@@ -2762,122 +2762,6 @@ define double @v_sqrt_f64_afn_nnan_ninf_nsz(double %x) {
27622762
ret double %result
27632763
}
27642764

2765-
define double @v_sqrt_f64__approx_func_fp_math(double %x) #2 {
2766-
; GFX6-SDAG-LABEL: v_sqrt_f64__approx_func_fp_math:
2767-
; GFX6-SDAG: ; %bb.0:
2768-
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2769-
; GFX6-SDAG-NEXT: s_mov_b32 s4, 0
2770-
; GFX6-SDAG-NEXT: s_brev_b32 s5, 8
2771-
; GFX6-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
2772-
; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, 0x100
2773-
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2774-
; GFX6-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
2775-
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
2776-
; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
2777-
; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
2778-
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
2779-
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
2780-
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
2781-
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
2782-
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
2783-
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
2784-
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
2785-
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
2786-
; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
2787-
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
2788-
; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
2789-
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
2790-
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
2791-
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
2792-
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
2793-
;
2794-
; GFX8-SDAG-LABEL: v_sqrt_f64__approx_func_fp_math:
2795-
; GFX8-SDAG: ; %bb.0:
2796-
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2797-
; GFX8-SDAG-NEXT: s_mov_b32 s4, 0
2798-
; GFX8-SDAG-NEXT: s_brev_b32 s5, 8
2799-
; GFX8-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
2800-
; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, 0x100
2801-
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2802-
; GFX8-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
2803-
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
2804-
; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
2805-
; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
2806-
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
2807-
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
2808-
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
2809-
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
2810-
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
2811-
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
2812-
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
2813-
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
2814-
; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
2815-
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
2816-
; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
2817-
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
2818-
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
2819-
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
2820-
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
2821-
;
2822-
; GFX6-GISEL-LABEL: v_sqrt_f64__approx_func_fp_math:
2823-
; GFX6-GISEL: ; %bb.0:
2824-
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2825-
; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, 0
2826-
; GFX6-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
2827-
; GFX6-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
2828-
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
2829-
; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
2830-
; GFX6-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
2831-
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
2832-
; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
2833-
; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
2834-
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
2835-
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
2836-
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
2837-
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
2838-
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
2839-
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
2840-
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
2841-
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
2842-
; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
2843-
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
2844-
; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
2845-
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
2846-
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
2847-
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
2848-
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
2849-
;
2850-
; GFX8-GISEL-LABEL: v_sqrt_f64__approx_func_fp_math:
2851-
; GFX8-GISEL: ; %bb.0:
2852-
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2853-
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0
2854-
; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
2855-
; GFX8-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
2856-
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
2857-
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
2858-
; GFX8-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
2859-
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
2860-
; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
2861-
; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
2862-
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
2863-
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
2864-
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
2865-
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
2866-
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
2867-
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
2868-
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
2869-
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
2870-
; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
2871-
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
2872-
; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
2873-
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
2874-
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
2875-
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
2876-
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
2877-
%result = call nsz double @llvm.sqrt.f64(double %x)
2878-
ret double %result
2879-
}
2880-
28812765
define double @v_sqrt_f64__enough_unsafe_attrs(double %x) #3 {
28822766
; GFX6-SDAG-LABEL: v_sqrt_f64__enough_unsafe_attrs:
28832767
; GFX6-SDAG: ; %bb.0:
@@ -3580,8 +3464,7 @@ declare i32 @llvm.amdgcn.readfirstlane(i32) #1
35803464

35813465
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
35823466
attributes #1 = { convergent nounwind willreturn memory(none) }
3583-
attributes #2 = { "approx-func-fp-math"="true" }
3584-
attributes #3 = { "approx-func-fp-math"="true" "no-nans-fp-math"="true" "no-infs-fp-math"="true" }
3467+
attributes #3 = { "no-nans-fp-math"="true" "no-infs-fp-math"="true" }
35853468
attributes #4 = { "unsafe-fp-math"="true" }
35863469
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
35873470
; GFX6: {{.*}}

‎llvm/test/CodeGen/AMDGPU/llvm.exp2.ll‎

Lines changed: 0 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -1583,104 +1583,6 @@ define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
15831583
ret float %result
15841584
}
15851585

1586-
define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
1587-
; SI-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
1588-
; SI-SDAG: ; %bb.0:
1589-
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1590-
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1591-
; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1592-
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1593-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1594-
; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1595-
; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
1596-
; SI-SDAG-NEXT: v_not_b32_e32 v1, 63
1597-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1598-
; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
1599-
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
1600-
;
1601-
; SI-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
1602-
; SI-GISEL: ; %bb.0:
1603-
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1604-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1605-
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1606-
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1607-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1608-
; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1609-
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
1610-
; SI-GISEL-NEXT: v_not_b32_e32 v1, 63
1611-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1612-
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
1613-
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
1614-
;
1615-
; VI-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
1616-
; VI-SDAG: ; %bb.0:
1617-
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1618-
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1619-
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1620-
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1621-
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1622-
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1623-
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
1624-
; VI-SDAG-NEXT: v_not_b32_e32 v1, 63
1625-
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1626-
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
1627-
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
1628-
;
1629-
; VI-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
1630-
; VI-GISEL: ; %bb.0:
1631-
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1632-
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1633-
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1634-
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1635-
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1636-
; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1637-
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
1638-
; VI-GISEL-NEXT: v_not_b32_e32 v1, 63
1639-
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1640-
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
1641-
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
1642-
;
1643-
; GFX900-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
1644-
; GFX900-SDAG: ; %bb.0:
1645-
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1646-
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1647-
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1648-
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1649-
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1650-
; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1651-
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
1652-
; GFX900-SDAG-NEXT: v_not_b32_e32 v1, 63
1653-
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1654-
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
1655-
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
1656-
;
1657-
; GFX900-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
1658-
; GFX900-GISEL: ; %bb.0:
1659-
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1660-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1661-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1662-
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1663-
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1664-
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1665-
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
1666-
; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63
1667-
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1668-
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
1669-
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
1670-
;
1671-
; R600-LABEL: v_exp2_f32_approx_fn_attr:
1672-
; R600: ; %bb.0:
1673-
; R600-NEXT: CF_END
1674-
; R600-NEXT: PAD
1675-
;
1676-
; CM-LABEL: v_exp2_f32_approx_fn_attr:
1677-
; CM: ; %bb.0:
1678-
; CM-NEXT: CF_END
1679-
; CM-NEXT: PAD
1680-
%result = call float @llvm.exp2.f32(float %in)
1681-
ret float %result
1682-
}
1683-
16841586
define float @v_exp2_f32_ninf(float %in) {
16851587
; SI-SDAG-LABEL: v_exp2_f32_ninf:
16861588
; SI-SDAG: ; %bb.0:

‎llvm/test/CodeGen/AMDGPU/llvm.log2.ll‎

Lines changed: 0 additions & 123 deletions
Original file line numberDiff line numberDiff line change
@@ -2030,129 +2030,6 @@ define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
20302030
ret float %result
20312031
}
20322032

2033-
define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
2034-
; SI-SDAG-LABEL: v_log2_f32_approx_fn_attr:
2035-
; SI-SDAG: ; %bb.0:
2036-
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2037-
; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
2038-
; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2039-
; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
2040-
; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
2041-
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
2042-
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
2043-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
2044-
; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
2045-
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2046-
;
2047-
; SI-GISEL-LABEL: v_log2_f32_approx_fn_attr:
2048-
; SI-GISEL: ; %bb.0:
2049-
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2050-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
2051-
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2052-
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
2053-
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
2054-
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
2055-
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
2056-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
2057-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
2058-
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
2059-
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2060-
;
2061-
; VI-SDAG-LABEL: v_log2_f32_approx_fn_attr:
2062-
; VI-SDAG: ; %bb.0:
2063-
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2064-
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
2065-
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2066-
; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
2067-
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
2068-
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
2069-
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
2070-
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
2071-
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
2072-
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2073-
;
2074-
; VI-GISEL-LABEL: v_log2_f32_approx_fn_attr:
2075-
; VI-GISEL: ; %bb.0:
2076-
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2077-
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
2078-
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2079-
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
2080-
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
2081-
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
2082-
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
2083-
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
2084-
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
2085-
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
2086-
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2087-
;
2088-
; GFX900-SDAG-LABEL: v_log2_f32_approx_fn_attr:
2089-
; GFX900-SDAG: ; %bb.0:
2090-
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2091-
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
2092-
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2093-
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
2094-
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
2095-
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
2096-
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
2097-
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
2098-
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
2099-
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2100-
;
2101-
; GFX900-GISEL-LABEL: v_log2_f32_approx_fn_attr:
2102-
; GFX900-GISEL: ; %bb.0:
2103-
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2104-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
2105-
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2106-
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
2107-
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
2108-
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
2109-
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
2110-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
2111-
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
2112-
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
2113-
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2114-
;
2115-
; GFX1100-SDAG-LABEL: v_log2_f32_approx_fn_attr:
2116-
; GFX1100-SDAG: ; %bb.0:
2117-
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2118-
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
2119-
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
2120-
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
2121-
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
2122-
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
2123-
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
2124-
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
2125-
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
2126-
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
2127-
;
2128-
; GFX1100-GISEL-LABEL: v_log2_f32_approx_fn_attr:
2129-
; GFX1100-GISEL: ; %bb.0:
2130-
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2131-
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
2132-
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
2133-
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
2134-
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
2135-
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
2136-
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
2137-
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
2138-
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
2139-
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
2140-
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
2141-
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
2142-
;
2143-
; R600-LABEL: v_log2_f32_approx_fn_attr:
2144-
; R600: ; %bb.0:
2145-
; R600-NEXT: CF_END
2146-
; R600-NEXT: PAD
2147-
;
2148-
; CM-LABEL: v_log2_f32_approx_fn_attr:
2149-
; CM: ; %bb.0:
2150-
; CM-NEXT: CF_END
2151-
; CM-NEXT: PAD
2152-
%result = call float @llvm.log2.f32(float %in)
2153-
ret float %result
2154-
}
2155-
21562033
define float @v_log2_f32_ninf(float %in) {
21572034
; SI-SDAG-LABEL: v_log2_f32_ninf:
21582035
; SI-SDAG: ; %bb.0:

‎llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,4 +29,4 @@ entry:
2929
ret void
3030
}
3131

32-
attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "approx-func-fp-math"="false" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
32+
attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }

‎llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,5 +30,5 @@ entry:
3030
ret i32 0
3131
}
3232

33-
attributes #0 = { convergent noinline norecurse optnone "approx-func-fp-math"="true" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
34-
attributes #1 = { alwaysinline convergent mustprogress norecurse nounwind "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
33+
attributes #0 = { convergent noinline norecurse optnone "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
34+
attributes #1 = { alwaysinline convergent mustprogress norecurse nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }

‎llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,5 +40,5 @@ entry:
4040
ret i32 0
4141
}
4242

43-
attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
44-
attributes #1 = { convergent noinline norecurse optnone "approx-func-fp-math"="true" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
43+
attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
44+
attributes #1 = { convergent noinline norecurse optnone "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }

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