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[X86] Cleanup SFENCE/MFENCE schedules
Remove unnecessary overrides. UOp + Port usage confirmed by augner/uops.info
1 parent 124b1f8 commit 37aebcf

23 files changed

+46
-104
lines changed

‎llvm/lib/Target/X86/X86SchedBroadwell.td‎

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -615,7 +615,7 @@ def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; }
615615
def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; }
616616

617617
// Fence instructions.
618-
def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
618+
def : WriteRes<WriteFence, [BWPort23, BWPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
619619

620620
// Nop, not very useful expect it provides a model for nops!
621621
def : WriteRes<WriteNop, []>;
@@ -722,7 +722,6 @@ def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
722722
let ReleaseAtCycles = [2];
723723
}
724724
def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
725-
MFENCE,
726725
WAIT,
727726
XGETBV)>;
728727

@@ -740,13 +739,6 @@ def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
740739
}
741740
def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
742741

743-
def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
744-
let Latency = 2;
745-
let NumMicroOps = 2;
746-
let ReleaseAtCycles = [1,1];
747-
}
748-
def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
749-
750742
def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
751743
let Latency = 2;
752744
let NumMicroOps = 2;

‎llvm/lib/Target/X86/X86SchedHaswell.td‎

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -627,7 +627,7 @@ def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
627627
def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
628628

629629
// Fence instructions.
630-
def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
630+
def : WriteRes<WriteFence, [HWPort23, HWPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
631631

632632
// Nop, not very useful expect it provides a model for nops!
633633
def : WriteRes<WriteNop, []>;
@@ -1054,13 +1054,6 @@ def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
10541054
def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
10551055
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
10561056

1057-
def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
1058-
let Latency = 2;
1059-
let NumMicroOps = 2;
1060-
let ReleaseAtCycles = [1,1];
1061-
}
1062-
def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
1063-
10641057
def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
10651058
let Latency = 2;
10661059
let NumMicroOps = 3;
@@ -1121,7 +1114,6 @@ def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
11211114
let ReleaseAtCycles = [2];
11221115
}
11231116
def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
1124-
MFENCE,
11251117
WAIT,
11261118
XGETBV)>;
11271119

‎llvm/lib/Target/X86/X86SchedIceLake.td‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -607,7 +607,7 @@ defm : ICXWriteResPair<WriteVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bi
607607
def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
608608

609609
// Fence instructions.
610-
def : WriteRes<WriteFence, [ICXPort78, ICXPort49]>;
610+
def : WriteRes<WriteFence, [ICXPort78, ICXPort49]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
611611

612612
// Load/store MXCSR.
613613
def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
@@ -771,13 +771,6 @@ def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
771771
}
772772
def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>;
773773

774-
def ICXWriteResGroup21 : SchedWriteRes<[ICXPort49,ICXPort78]> {
775-
let Latency = 2;
776-
let NumMicroOps = 2;
777-
let ReleaseAtCycles = [1,1];
778-
}
779-
def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>;
780-
781774
def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
782775
let Latency = 2;
783776
let NumMicroOps = 2;
@@ -916,13 +909,6 @@ def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
916909
}
917910
def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>;
918911

919-
def ICXWriteResGroup43 : SchedWriteRes<[ICXPort49,ICXPort78]> {
920-
let Latency = 3;
921-
let NumMicroOps = 3;
922-
let ReleaseAtCycles = [1,2];
923-
}
924-
def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>;
925-
926912
def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
927913
let Latency = 2;
928914
let NumMicroOps = 3;

‎llvm/lib/Target/X86/X86SchedSandyBridge.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -588,7 +588,7 @@ def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency =
588588

589589
def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
590590
def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
591-
def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
591+
def : WriteRes<WriteFence, [SBPort23, SBPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
592592
def : WriteRes<WriteNop, []>;
593593

594594
// AVX2/FMA is not supported on that architecture, but we should define the basic

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -608,7 +608,7 @@ defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bi
608608
def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
609609

610610
// Fence instructions.
611-
def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
611+
def : WriteRes<WriteFence, [SKLPort23, SKLPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
612612

613613
// Load/store MXCSR.
614614
def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
@@ -738,13 +738,6 @@ def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
738738
}
739739
def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
740740

741-
def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
742-
let Latency = 2;
743-
let NumMicroOps = 2;
744-
let ReleaseAtCycles = [1,1];
745-
}
746-
def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
747-
748741
def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
749742
let Latency = 2;
750743
let NumMicroOps = 2;
@@ -834,13 +827,6 @@ def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
834827
}
835828
def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
836829

837-
def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
838-
let Latency = 3;
839-
let NumMicroOps = 3;
840-
let ReleaseAtCycles = [1,2];
841-
}
842-
def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
843-
844830
def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
845831
let Latency = 2;
846832
let NumMicroOps = 3;

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -602,7 +602,7 @@ defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bi
602602
def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
603603

604604
// Fence instructions.
605-
def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
605+
def : WriteRes<WriteFence, [SKXPort23, SKXPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
606606

607607
// Load/store MXCSR.
608608
def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
@@ -757,13 +757,6 @@ def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
757757
}
758758
def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
759759

760-
def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
761-
let Latency = 2;
762-
let NumMicroOps = 2;
763-
let ReleaseAtCycles = [1,1];
764-
}
765-
def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
766-
767760
def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
768761
let Latency = 2;
769762
let NumMicroOps = 2;
@@ -894,13 +887,6 @@ def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
894887
}
895888
def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
896889

897-
def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
898-
let Latency = 3;
899-
let NumMicroOps = 3;
900-
let ReleaseAtCycles = [1,2];
901-
}
902-
def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
903-
904890
def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
905891
let Latency = 2;
906892
let NumMicroOps = 3;

‎llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ xorps (%rax), %xmm2
298298
# CHECK-NEXT: 2 11 1.00 * rsqrtps (%rax), %xmm2
299299
# CHECK-NEXT: 1 5 1.00 rsqrtss %xmm0, %xmm2
300300
# CHECK-NEXT: 2 11 1.00 * rsqrtss (%rax), %xmm2
301-
# CHECK-NEXT: 1 1 1.00 * * U sfence
301+
# CHECK-NEXT: 2 1 1.00 * * U sfence
302302
# CHECK-NEXT: 1 1 1.00 shufps $1, %xmm0, %xmm2
303303
# CHECK-NEXT: 2 7 1.00 * shufps $1, (%rax), %xmm2
304304
# CHECK-NEXT: 1 14 14.00 sqrtps %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -464,13 +464,13 @@ xorpd (%rax), %xmm2
464464
# CHECK-NEXT: 2 28 22.00 * divpd (%rax), %xmm2
465465
# CHECK-NEXT: 1 22 22.00 divsd %xmm0, %xmm2
466466
# CHECK-NEXT: 2 28 22.00 * divsd (%rax), %xmm2
467-
# CHECK-NEXT: 1 1 1.00 * * U lfence
467+
# CHECK-NEXT: 2 1 1.00 * * U lfence
468468
# CHECK-NEXT: 1 1 1.00 * * U maskmovdqu %xmm0, %xmm1
469469
# CHECK-NEXT: 1 3 1.00 maxpd %xmm0, %xmm2
470470
# CHECK-NEXT: 2 9 1.00 * maxpd (%rax), %xmm2
471471
# CHECK-NEXT: 1 3 1.00 maxsd %xmm0, %xmm2
472472
# CHECK-NEXT: 2 9 1.00 * maxsd (%rax), %xmm2
473-
# CHECK-NEXT: 1 1 1.00 * * U mfence
473+
# CHECK-NEXT: 2 1 1.00 * * U mfence
474474
# CHECK-NEXT: 1 3 1.00 minpd %xmm0, %xmm2
475475
# CHECK-NEXT: 2 9 1.00 * minpd (%rax), %xmm2
476476
# CHECK-NEXT: 1 3 1.00 minsd %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ xorps (%rax), %xmm2
298298
# CHECK-NEXT: 2 10 1.00 * rsqrtps (%rax), %xmm2
299299
# CHECK-NEXT: 1 5 1.00 rsqrtss %xmm0, %xmm2
300300
# CHECK-NEXT: 2 10 1.00 * rsqrtss (%rax), %xmm2
301-
# CHECK-NEXT: 2 2 0.33 * * U sfence
301+
# CHECK-NEXT: 2 1 1.00 * * U sfence
302302
# CHECK-NEXT: 1 1 1.00 shufps $1, %xmm0, %xmm2
303303
# CHECK-NEXT: 2 6 1.00 * shufps $1, (%rax), %xmm2
304304
# CHECK-NEXT: 1 11 7.00 sqrtps %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
333333

334334
# CHECK: Resource pressure per iteration:
335335
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
336-
# CHECK-NEXT: - 43.00 34.50 50.50 32.00 32.00 8.00 40.50 0.50 3.00
336+
# CHECK-NEXT: - 43.00 34.25 50.25 32.17 32.17 9.00 40.25 0.25 2.67
337337

338338
# CHECK: Resource pressure by instruction:
339339
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -441,7 +441,7 @@ xorps (%rax), %xmm2
441441
# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - rsqrtps (%rax), %xmm2
442442
# CHECK-NEXT: - - 1.00 - - - - - - - rsqrtss %xmm0, %xmm2
443443
# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - rsqrtss (%rax), %xmm2
444-
# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 - 0.25 0.25 0.33 sfence
444+
# CHECK-NEXT: - - - - 0.50 0.50 1.00 - - - sfence
445445
# CHECK-NEXT: - - - - - - - 1.00 - - shufps $1, %xmm0, %xmm2
446446
# CHECK-NEXT: - - - - 0.50 0.50 - 1.00 - - shufps $1, (%rax), %xmm2
447447
# CHECK-NEXT: - 7.00 1.00 - - - - - - - sqrtps %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -470,7 +470,7 @@ xorpd (%rax), %xmm2
470470
# CHECK-NEXT: 2 8 1.00 * maxpd (%rax), %xmm2
471471
# CHECK-NEXT: 1 3 1.00 maxsd %xmm0, %xmm2
472472
# CHECK-NEXT: 2 8 1.00 * maxsd (%rax), %xmm2
473-
# CHECK-NEXT: 2 2 0.50 * * U mfence
473+
# CHECK-NEXT: 2 1 1.00 * * U mfence
474474
# CHECK-NEXT: 1 3 1.00 minpd %xmm0, %xmm2
475475
# CHECK-NEXT: 2 8 1.00 * minpd (%rax), %xmm2
476476
# CHECK-NEXT: 1 3 1.00 minsd %xmm0, %xmm2
@@ -689,7 +689,7 @@ xorpd (%rax), %xmm2
689689

690690
# CHECK: Resource pressure per iteration:
691691
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
692-
# CHECK-NEXT: - 78.00 70.75 95.75 63.17 63.17 14.00 117.25 2.25 4.67
692+
# CHECK-NEXT: - 78.00 70.25 95.25 63.67 63.67 15.00 116.75 1.75 4.67
693693

694694
# CHECK: Resource pressure by instruction:
695695
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -756,7 +756,7 @@ xorpd (%rax), %xmm2
756756
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - maxpd (%rax), %xmm2
757757
# CHECK-NEXT: - - - 1.00 - - - - - - maxsd %xmm0, %xmm2
758758
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - maxsd (%rax), %xmm2
759-
# CHECK-NEXT: - - 0.50 0.50 - - - 0.50 0.50 - mfence
759+
# CHECK-NEXT: - - - - 0.50 0.50 1.00 - - - mfence
760760
# CHECK-NEXT: - - - 1.00 - - - - - - minpd %xmm0, %xmm2
761761
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - minpd (%rax), %xmm2
762762
# CHECK-NEXT: - - - 1.00 - - - - - - minsd %xmm0, %xmm2

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