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[AArch64][llvm] Armv9.7-A: Add support for SVE2p3 CVT operations (llvm#163162)
Add instructions for SVE2p3 CVT operations: - FCVTZSN - FCVTZUN - SCVTF - SCVTFLT - UCVTF - UCVTFLT as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

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@@ -4639,6 +4639,15 @@ let Predicates = [HasSVE2p3_or_SME2p3] in {
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def SDOT_ZZZI_BtoH : sve_intx_dot_by_indexed_elem_x<0b0, "sdot">;
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def UDOT_ZZZI_BtoH : sve_intx_dot_by_indexed_elem_x<0b1, "udot">;
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// SVE2 fp convert, narrow and interleave to integer, rounding toward zero
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defm FCVTZSN_Z2Z : sve2_fp_to_int_downcvt<"fcvtzsn", 0b0>;
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defm FCVTZUN_Z2Z : sve2_fp_to_int_downcvt<"fcvtzun", 0b1>;
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// SVE2 signed/unsigned integer convert to floating-point
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defm SCVTF_ZZ : sve2_int_to_fp_upcvt<"scvtf", 0b00>;
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defm SCVTFLT_ZZ : sve2_int_to_fp_upcvt<"scvtflt", 0b10>;
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defm UCVTF_ZZ : sve2_int_to_fp_upcvt<"ucvtf", 0b01>;
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defm UCVTFLT_ZZ : sve2_int_to_fp_upcvt<"ucvtflt", 0b11>;
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} // End HasSME2p3orSVE2p3
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

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@@ -11300,3 +11300,49 @@ class sve_int_mla_cpa<string asm>
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let ElementSize = ZPR64.ElementSize;
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}
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//===----------------------------------------------------------------------===//
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// FP to Int down-converts
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//===----------------------------------------------------------------------===//
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class sve2_fp_to_int_downcvt<string asm, ZPRRegOp ZdRC, RegisterOperand ZSrcOp, bits<2> size, bit U>
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: I<(outs ZdRC:$Zd), (ins ZSrcOp:$Zn),
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asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
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bits<5> Zd;
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bits<4> Zn;
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let Inst{31-24} = 0b01100101;
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let Inst{23-22} = size;
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let Inst{21-11} = 0b00110100110;
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let Inst{10} = U;
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let Inst{9-6} = Zn;
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let Inst{5} = 0b0;
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let Inst{4-0} = Zd;
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}
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multiclass sve2_fp_to_int_downcvt<string asm, bit U> {
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def _HtoB : sve2_fp_to_int_downcvt<asm, ZPR8, ZZ_h_mul_r, 0b01, U>;
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def _StoH : sve2_fp_to_int_downcvt<asm, ZPR16, ZZ_s_mul_r, 0b10, U>;
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def _DtoS : sve2_fp_to_int_downcvt<asm, ZPR32, ZZ_d_mul_r, 0b11, U>;
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}
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//===----------------------------------------------------------------------===//
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// Int to FP up-converts
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//===----------------------------------------------------------------------===//
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class sve2_int_to_fp_upcvt<string asm, ZPRRegOp ZdRC, ZPRRegOp ZnRC,
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bits<2> size, bits<2> U>
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: I<(outs ZdRC:$Zd), (ins ZnRC:$Zn),
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asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zn;
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let Inst{31-24} = 0b01100101;
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let Inst{23-22} = size;
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let Inst{21-12} = 0b0011000011;
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let Inst{11-10} = U;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve2_int_to_fp_upcvt<string asm, bits<2> U> {
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def _BtoH : sve2_int_to_fp_upcvt<asm, ZPR16, ZPR8, 0b01, U>;
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def _HtoS : sve2_int_to_fp_upcvt<asm, ZPR32, ZPR16, 0b10, U>;
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def _StoD : sve2_int_to_fp_upcvt<asm, ZPR64, ZPR32, 0b11, U>;
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}

‎llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid operand for instruction
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fcvtzsn z0.b, { z0.b, z1.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzsn z0.b, { z0.b, z1.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzsn z0.h, { z0.h, z1.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzsn z0.h, { z0.h, z1.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzsn z0.s, { z0.s, z1.s }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzsn z0.s, { z0.s, z1.s }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzsn z0.b, { z1.h, z2.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: fcvtzsn z0.b, { z1.h, z2.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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fcvtzsn z0.b, { z2.h, z3.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fcvtzsn z0.b, { z2.h, z3.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid operand for instruction
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fcvtzun z0.b, { z0.b, z1.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzun z0.b, { z0.b, z1.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzun z0.h, { z0.h, z1.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzun z0.h, { z0.h, z1.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzun z0.s, { z0.s, z1.s }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzun z0.s, { z0.s, z1.s }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzun z0.b, { z1.h, z2.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: fcvtzun z0.b, { z1.h, z2.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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fcvtzun z0.b, { z2.h, z3.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fcvtzun z0.b, { z2.h, z3.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid element width
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scvtf z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtf z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtf z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf z0.s, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtf z0.s, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtf z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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scvtf z0.h, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: scvtf z0.h, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid element width
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scvtflt z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtflt z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtflt z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtflt z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtflt z0.s, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtflt z0.s, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtflt z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtflt z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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scvtflt z0.h, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: scvtflt z0.h, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid element width
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ucvtf z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtf z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtf z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtf z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtf z0.s, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtf z0.s, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtf z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtf z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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ucvtf z0.h, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ucvtf z0.h, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid element width
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ucvtflt z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtflt z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtflt z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtflt z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtflt z0.s, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtflt z0.s, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtflt z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ucvtflt z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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ucvtflt z0.h, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ucvtflt z0.h, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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