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[AArch64][SVE] Avoid redundant extend of unsigned i8/i16 extracts. (llvm#165863)
Extracts of unsigned i8 or i16 elements from the bottom 128 bits of a scalable register lead to the implied zero-extend being transformed to an AND mask. The mask is redundant since UMOV already zeroes the high bits of the destination register. For example: ```c int foo(svuint8_t x) {   return x[3]; } ``` Currently: ```gas foo:   umov    w8, v0.b[3]   and     w0, w8, #0xff   ret ``` Becomes: ```gas foo:   umov    w0, v0.b[3]   ret ```
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

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Original file line numberDiff line numberDiff line change
@@ -3597,6 +3597,18 @@ let Predicates = [HasSVE_or_SME] in {
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def : Pat<(sext (i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index))),
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(SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
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// Extracts of ``unsigned'' i8 or i16 elements lead to the zero-extend being
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// transformed to an AND mask. The mask is redundant since UMOV already zeroes
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// the high bits of the destination register.
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def : Pat<(i32 (and (vector_extract nxv16i8:$vec, VectorIndexB:$index), 0xff)),
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(UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
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def : Pat<(i32 (and (vector_extract nxv8i16:$vec, VectorIndexH:$index), 0xffff)),
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(UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
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def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)))), (i64 0xff))),
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(SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)), sub_32)>;
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def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)))), (i64 0xffff))),
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(SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)), sub_32)>;
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} // End HasNEON
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// Extract first element from vector.

‎llvm/test/CodeGen/AArch64/sve-extract-element.ll‎

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Original file line numberDiff line numberDiff line change
@@ -12,6 +12,26 @@ define i8 @test_lane0_16xi8(<vscale x 16 x i8> %a) #0 {
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ret i8 %b
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}
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define i32 @test_lane0_16xi8_zext_i32(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane0_16xi8_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.b[0]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 16 x i8> %a, i32 0
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%c = zext i8 %b to i32
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ret i32 %c
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}
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define i64 @test_lane0_16xi8_zext_i64(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane0_16xi8_zext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.b[0]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 16 x i8> %a, i32 0
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%c = zext i8 %b to i64
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ret i64 %c
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}
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define i8 @test_lane15_16xi8(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane15_16xi8:
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; CHECK: // %bb.0:
@@ -21,6 +41,26 @@ define i8 @test_lane15_16xi8(<vscale x 16 x i8> %a) #0 {
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ret i8 %b
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}
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define i32 @test_lane15_16xi8_zext_i32(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane15_16xi8_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.b[15]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 16 x i8> %a, i32 15
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%c = zext i8 %b to i32
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ret i32 %c
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}
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define i64 @test_lane15_16xi8_zext_i64(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane15_16xi8_zext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.b[15]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 16 x i8> %a, i32 15
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%c = zext i8 %b to i64
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ret i64 %c
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}
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define i8 @test_lane16_16xi8(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane16_16xi8:
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; CHECK: // %bb.0:
@@ -31,6 +71,32 @@ define i8 @test_lane16_16xi8(<vscale x 16 x i8> %a) #0 {
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ret i8 %b
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}
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; FIXME: FMOV+AND -> UMOV.
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define i32 @test_lane16_16xi8_zext_i32(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane16_16xi8_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.b, z0.b[16]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0xff
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 16 x i8> %a, i32 16
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%c = zext i8 %b to i32
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ret i32 %c
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}
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; FIXME: FMOV+AND -> UMOV.
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define i64 @test_lane16_16xi8_zext_i64(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: test_lane16_16xi8_zext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.b, z0.b[16]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 16 x i8> %a, i32 16
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%c = zext i8 %b to i64
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ret i64 %c
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}
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define i16 @test_lane0_8xi16(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane0_8xi16:
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; CHECK: // %bb.0:
@@ -40,6 +106,26 @@ define i16 @test_lane0_8xi16(<vscale x 8 x i16> %a) #0 {
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ret i16 %b
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}
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define i32 @test_lane0_8xi16_zext_i32(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane0_8xi16_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 8 x i16> %a, i32 0
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%c = zext i16 %b to i32
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ret i32 %c
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}
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define i64 @test_lane0_8xi16_zext_i64(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane0_8xi16_zext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 8 x i16> %a, i32 0
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%c = zext i16 %b to i64
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ret i64 %c
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}
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define i16 @test_lane7_8xi16(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane7_8xi16:
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; CHECK: // %bb.0:
@@ -49,6 +135,26 @@ define i16 @test_lane7_8xi16(<vscale x 8 x i16> %a) #0 {
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ret i16 %b
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}
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define i32 @test_lane7_8xi16_zext_i32(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane7_8xi16_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.h[7]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 8 x i16> %a, i32 7
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%c = zext i16 %b to i32
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ret i32 %c
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}
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define i64 @test_lane7_8xi16_zext_i64(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane7_8xi16_zext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umov w0, v0.h[7]
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 8 x i16> %a, i32 7
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%c = zext i16 %b to i64
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ret i64 %c
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}
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define i16 @test_lane8_8xi16(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane8_8xi16:
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; CHECK: // %bb.0:
@@ -59,6 +165,32 @@ define i16 @test_lane8_8xi16(<vscale x 8 x i16> %a) #0 {
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ret i16 %b
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}
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; FIXME: FMOV+AND -> UMOV.
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define i32 @test_lane8_8xi16_zext_i32(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane8_8xi16_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.h, z0.h[8]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0xffff
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 8 x i16> %a, i32 8
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%c = zext i16 %b to i32
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ret i32 %c
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}
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; FIXME: FMOV+AND -> UMOV.
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define i64 @test_lane8_8xi16_zext_i64(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: test_lane8_8xi16_zext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.h, z0.h[8]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 8 x i16> %a, i32 8
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%c = zext i16 %b to i64
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ret i64 %c
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}
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define i32 @test_lane0_4xi32(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: test_lane0_4xi32:
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; CHECK: // %bb.0:

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