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arm-trusted-firmware-mediatek: import patchset for Fidelix flash on SNFI
Import pending patches to set pinconf settings for SPI-NAND pins on MT7622 identical to what the old proprietary preloader did. Should further increase the reliability of some SNFI-attached SPI-NAND flash chips. Link: mtk-openwrt/arm-trusted-firmware#7 Signed-off-by: Daniel Golle <[email protected]>
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‎package/boot/arm-trusted-firmware-mediatek/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
include $(TOPDIR)/rules.mk
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1111
PKG_NAME:=arm-trusted-firmware-mediatek
12-
PKG_RELEASE:=1
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PKG_RELEASE:=2
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1414
PKG_SOURCE_PROTO:=git
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PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git

‎package/boot/arm-trusted-firmware-mediatek/patches/0001-mediatek-snfi-FM35Q1GA-is-x4-only.patch‎

Lines changed: 23 additions & 0 deletions
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@@ -0,0 +1,23 @@
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From fb2a2b669ec9bbf5c448d4b56499bc83de075c93 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <[email protected]>
3+
Date: Thu, 29 Feb 2024 18:01:08 +0000
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Subject: [PATCH 1/3] mediatek: snfi: FM35Q1GA is x4-only
5+
6+
Dont allow x2 read and cache read operations on FM35Q1GA.
7+
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Signed-off-by: Daniel Golle <[email protected]>
9+
---
10+
plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c | 2 +-
11+
1 file changed, 1 insertion(+), 1 deletion(-)
12+
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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@@ -423,7 +423,7 @@ static const struct snand_flash_info sna
16+
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SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
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SNAND_MEMORG_1G_2K_64,
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- &snand_cap_read_from_cache_x4,
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+ &snand_cap_read_from_cache_x4_only,
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&snand_cap_program_load_x4),
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SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),

‎package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-snfi-adjust-pin-drive-strength-for-Fidelix-.patch‎

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,99 @@
1+
From 6470986f037880ce76960c369d6e5a5270e7ce32 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <[email protected]>
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Date: Sun, 10 Mar 2024 15:39:07 +0000
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Subject: [PATCH 2/3] mediatek: snfi: adjust pin drive strength for Fidelix
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SPI-NAND
6+
7+
It seems like we might need to adjust the pin driver strength to 12mA
8+
for Fidelix SPI-NAND chip on MT7622 to avoid SPI data corruption on
9+
some devices.
10+
11+
Signed-off-by: Daniel Golle <[email protected]>
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---
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.../apsoc_common/drivers/snfi/mtk-snand-def.h | 7 +++++
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.../apsoc_common/drivers/snfi/mtk-snand-ids.c | 4 ++-
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.../apsoc_common/drivers/snfi/mtk-snand.c | 30 +++++++++++++++++++
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3 files changed, 40 insertions(+), 1 deletion(-)
17+
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
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+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
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@@ -86,6 +86,12 @@ struct snand_mem_org {
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typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
23+
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+enum snand_drv {
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+ SNAND_DRV_NO_CHANGE = 0,
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+ SNAND_DRV_8mA = 8,
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+ SNAND_DRV_12mA = 12,
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+};
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+
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struct snand_flash_info {
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const char *model;
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struct snand_id id;
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@@ -93,6 +99,7 @@ struct snand_flash_info {
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const struct snand_io_cap *cap_rd;
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const struct snand_io_cap *cap_pl;
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snand_select_die_t select_die;
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+ enum snand_drv drv;
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};
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#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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@@ -424,7 +424,9 @@ static const struct snand_flash_info sna
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SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
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SNAND_MEMORG_1G_2K_64,
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&snand_cap_read_from_cache_x4_only,
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- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
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+ NULL,
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+ SNAND_DRV_12mA),
51+
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SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
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SNAND_MEMORG_1G_2K_128,
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
55+
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
56+
@@ -1845,6 +1845,33 @@ static int mtk_snand_id_probe(struct mtk
57+
return -EINVAL;
58+
}
59+
60+
+#define MT7622_GPIO_BASE (void *)0x10211000
61+
+#define MT7622_GPIO_DRIV(x) (MT7622_GPIO_BASE + 0x900 + 0x10 * x)
62+
+
63+
+void mtk_mt7622_snand_adjust_drive(void *dev, enum snand_drv drv)
64+
+{
65+
+ uint32_t e4, e8;
66+
+
67+
+ e4 = readl(MT7622_GPIO_DRIV(6)) & ~(0x3f00);
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+ e8 = readl(MT7622_GPIO_DRIV(7)) & ~(0x3f00);
69+
+
70+
+ switch (drv) {
71+
+ case SNAND_DRV_8mA:
72+
+ e4 |= 0x3f00;
73+
+ break;
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+ case SNAND_DRV_12mA:
75+
+ e8 |= 0x3f00;
76+
+ break;
77+
+ default:
78+
+ return;
79+
+ }
80+
+
81+
+ snand_log_chip(dev, "adjusting SPI-NAND pin drive strength to %umA\n", drv);
82+
+
83+
+ writel(e4, MT7622_GPIO_DRIV(6));
84+
+ writel(e8, MT7622_GPIO_DRIV(7));
85+
+}
86+
+
87+
int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
88+
struct mtk_snand **psnf)
89+
{
90+
@@ -1888,6 +1915,9 @@ int mtk_snand_init(void *dev, const stru
91+
if (ret)
92+
return ret;
93+
94+
+ if (pdata->soc == SNAND_SOC_MT7622 && snand_info->drv)
95+
+ mtk_mt7622_snand_adjust_drive(dev, snand_info->drv);
96+
+
97+
rawpage_size = snand_info->memorg.pagesize +
98+
snand_info->memorg.sparesize;
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‎package/boot/arm-trusted-firmware-mediatek/patches/0003-mediatek-snfi-adjust-drive-strength-to-12mA-like-old.patch‎

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,135 @@
1+
From 40a3661bebb3d738ab95b7de66e9d8382d5b9ab1 Mon Sep 17 00:00:00 2001
2+
From: Daniel Golle <[email protected]>
3+
Date: Sun, 10 Mar 2024 17:48:09 +0000
4+
Subject: [PATCH 3/3] mediatek: snfi: adjust drive strength to 12mA like old
5+
loader does
6+
7+
In addition to FM35X1GA, also change the driver strength to 12mA for
8+
all chips where this is done by the old/legacy U-Boot:
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* Winbond 512Mb
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* Winbond 1Gb
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* Winbond 2Gb
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* GD5F4GQ4UBYIG
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* GD5F4GQ4UAYIG
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* GD5F1GQ4UX
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* GD5F1GQ4UE
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* GD5F2GQ4UX
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* GD5F2GQ4UE
18+
19+
Signed-off-by: Daniel Golle <[email protected]>
20+
---
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.../apsoc_common/drivers/snfi/mtk-snand-ids.c | 59 ++++++++++++++-----
22+
1 file changed, 44 insertions(+), 15 deletions(-)
23+
24+
--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
25+
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
26+
@@ -80,65 +80,94 @@ static const struct snand_flash_info sna
27+
SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),
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SNAND_MEMORG_512M_2K_64,
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&snand_cap_read_from_cache_quad,
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- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
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+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),
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SNAND_MEMORG_1G_2K_64,
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&snand_cap_read_from_cache_quad,
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- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
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+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),
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SNAND_MEMORG_2G_2K_64_2D,
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&snand_cap_read_from_cache_quad,
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&snand_cap_program_load_x4,
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- mtk_snand_winbond_select_die),
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+ mtk_snand_winbond_select_die,
47+
+ SNAND_DRV_12mA),
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SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),
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SNAND_MEMORG_2G_2K_128,
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&snand_cap_read_from_cache_quad,
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- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
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+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),
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SNAND_MEMORG_1G_2K_64,
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&snand_cap_read_from_cache_quad_q2d,
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- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
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+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),
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SNAND_MEMORG_1G_2K_128,
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&snand_cap_read_from_cache_quad_q2d,
66+
- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
68+
+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),
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SNAND_MEMORG_1G_2K_64,
72+
&snand_cap_read_from_cache_quad_q2d,
73+
- &snand_cap_program_load_x4),
74+
+ &snand_cap_program_load_x4,
75+
+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),
78+
SNAND_MEMORG_1G_2K_64,
79+
&snand_cap_read_from_cache_quad_q2d,
80+
- &snand_cap_program_load_x4),
81+
+ &snand_cap_program_load_x4,
82+
+ NULL,
83+
+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
85+
SNAND_MEMORG_2G_2K_128,
86+
&snand_cap_read_from_cache_quad_q2d,
87+
- &snand_cap_program_load_x4),
88+
+ &snand_cap_program_load_x4,
89+
+ NULL,
90+
+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),
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SNAND_MEMORG_2G_2K_64,
93+
&snand_cap_read_from_cache_quad_a8d,
94+
- &snand_cap_program_load_x4),
95+
+ &snand_cap_program_load_x4,
96+
+ NULL,
97+
+ SNAND_DRV_12mA),
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SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),
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SNAND_MEMORG_2G_2K_64,
100+
&snand_cap_read_from_cache_quad_q2d,
101+
- &snand_cap_program_load_x4),
102+
+ &snand_cap_program_load_x4,
103+
+ NULL,
104+
+ SNAND_DRV_12mA),
105+
SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),
106+
SNAND_MEMORG_4G_4K_256,
107+
&snand_cap_read_from_cache_quad_q2d,
108+
- &snand_cap_program_load_x4),
109+
+ &snand_cap_program_load_x4,
110+
+ NULL,
111+
+ SNAND_DRV_12mA),
112+
SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),
113+
SNAND_MEMORG_4G_2K_64,
114+
&snand_cap_read_from_cache_quad_q2d,
115+
- &snand_cap_program_load_x4),
116+
+ &snand_cap_program_load_x4,
117+
+ NULL,
118+
+ SNAND_DRV_12mA),
119+
SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),
120+
SNAND_MEMORG_2G_2K_128,
121+
&snand_cap_read_from_cache_quad_a8d,
122+
- &snand_cap_program_load_x4),
123+
+ &snand_cap_program_load_x4,
124+
+ NULL,
125+
+ SNAND_DRV_12mA),
126+
SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),
127+
SNAND_MEMORG_4G_4K_256,
128+
&snand_cap_read_from_cache_quad_q2d,
129+
- &snand_cap_program_load_x4),
130+
+ &snand_cap_program_load_x4,
131+
+ NULL,
132+
+ SNAND_DRV_12mA),
133+
134+
SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),
135+
SNAND_MEMORG_1G_2K_64,

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