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1 parent a70c435 commit 2af3cdcCopy full SHA for 2af3cdc
llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -877,8 +877,6 @@ class ExegesisRISCVTarget : public ExegesisTarget {
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// Setting up the correct FRM.
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PM.add(createRISCVInsertReadWriteCSRPass());
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PM.add(createRISCVInsertWriteVXRMPass());
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- // This will expand PseudoVSETVL* instructions.
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- PM.add(createRISCVExpandPseudoPass());
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// This will assign physical register to the result of VSETVLI instructions
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// that produce VLMAX.
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PM.add(exegesis::createRISCVPostprocessingPass());
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