@@ -72,17 +72,18 @@ class _MFIFO {
7272    }
7373
7474    void  registerCore () {
75-          if  (!__isFreeRTOS) { 
76-              multicore_fifo_clear_irq ();
75+ # ifndef  __FREERTOS 
76+         multicore_fifo_clear_irq ();
7777#ifdef  PICO_RP2350
78-              irq_set_exclusive_handler (SIO_IRQ_FIFO, _irq);
79-              irq_set_enabled (SIO_IRQ_FIFO, true );
78+         irq_set_exclusive_handler (SIO_IRQ_FIFO, _irq);
79+         irq_set_enabled (SIO_IRQ_FIFO, true );
8080#else 
81-              irq_set_exclusive_handler (SIO_IRQ_PROC0 + get_core_num (), _irq);
82-              irq_set_enabled (SIO_IRQ_PROC0 + get_core_num (), true );
81+         irq_set_exclusive_handler (SIO_IRQ_PROC0 + get_core_num (), _irq);
82+         irq_set_enabled (SIO_IRQ_PROC0 + get_core_num (), true );
8383#endif 
84-         } 
84+ # else 
8585        //  FreeRTOS port.c will handle the IRQ hooking
86+ #endif 
8687    }
8788
8889    void  push (uint32_t  val) {
@@ -113,14 +114,14 @@ class _MFIFO {
113114        if  (!_multicore) {
114115            return ;
115116        }
116-          if  (__isFreeRTOS) { 
117-              __freertos_idle_other_core ();
118-         }  else  { 
119-              mutex_enter_blocking (&_idleMutex);
120-              __otherCoreIdled = false ;
121-              multicore_fifo_push_blocking (_GOTOSLEEP);
122-              while  (!__otherCoreIdled) { /*  noop */   }
123-         } 
117+ # ifdef  __FREERTOS 
118+         __freertos_idle_other_core ();
119+ # else 
120+         mutex_enter_blocking (&_idleMutex);
121+         __otherCoreIdled = false ;
122+         multicore_fifo_push_blocking (_GOTOSLEEP);
123+         while  (!__otherCoreIdled) { /*  noop */   }
124+ # endif 
124125    }
125126
126127    void  resumeOtherCore () {
@@ -129,9 +130,9 @@ class _MFIFO {
129130        }
130131        mutex_exit (&_idleMutex);
131132        __otherCoreIdled = false ;
132-          if  (__isFreeRTOS) { 
133-              __freertos_resume_other_core ();
134-         } 
133+ # ifdef  __FREERTOS 
134+         __freertos_resume_other_core ();
135+ # endif 
135136
136137        //  Other core will exit busy-loop and return to operation
137138        //  once __otherCoreIdled == false.
@@ -151,18 +152,18 @@ class _MFIFO {
151152
152153private: 
153154    static  void  __no_inline_not_in_flash_func (_irq)() {
154-         if  (!__isFreeRTOS) {
155-             multicore_fifo_clear_irq ();
156-             noInterrupts (); //  We need total control, can't run anything
157-             while  (multicore_fifo_rvalid ()) {
158-                 if  (_GOTOSLEEP == multicore_fifo_pop_blocking ()) {
159-                     __otherCoreIdled = true ;
160-                     while  (__otherCoreIdled) { /*  noop */   }
161-                     break ;
162-                 }
155+ #ifndef  __FREERTOS
156+         multicore_fifo_clear_irq ();
157+         noInterrupts (); //  We need total control, can't run anything
158+         while  (multicore_fifo_rvalid ()) {
159+             if  (_GOTOSLEEP == multicore_fifo_pop_blocking ()) {
160+                 __otherCoreIdled = true ;
161+                 while  (__otherCoreIdled) { /*  noop */   }
162+                 break ;
163163            }
164-             interrupts ();
165164        }
165+         interrupts ();
166+ #endif 
166167    }
167168
168169    bool  _multicore = false ;
@@ -192,23 +193,19 @@ class RP2040 {
192193
193194    void  begin (int  cpuid) {
194195        _epoch[cpuid] = 0 ;
195- #if  !defined(__riscv) && !defined(__PROFILE)
196-         if  (!__isFreeRTOS) {
197-             //  Enable SYSTICK exception
198-             exception_set_exclusive_handler (SYSTICK_EXCEPTION, _SystickHandler);
199-             systick_hw->csr  = 0x7 ;
200-             systick_hw->rvr  = 0x00FFFFFF ;
201-         } else  {
202- #endif
203-             //  Only start 1 instance of the PIO SM
204-             if  (cpuid == 0 ) {
205-                 int  off = 0 ;
206-                 _ccountPgm = new  PIOProgram (&ccount_program);
207-                 _ccountPgm->prepare (&_pio, &_sm, &off);
208-                 ccount_program_init (_pio, _sm, off);
209-                 pio_sm_set_enabled (_pio, _sm, true );
210-             }
211- #if  !defined(__riscv) && !defined(__PROFILE)
196+ #if  !defined(__riscv) && !defined(__PROFILE) && !defined(__FREERTOS)
197+         //  Enable SYSTICK exception
198+         exception_set_exclusive_handler (SYSTICK_EXCEPTION, _SystickHandler);
199+         systick_hw->csr  = 0x7 ;
200+         systick_hw->rvr  = 0x00FFFFFF ;
201+ #else 
202+         //  Only start 1 instance of the PIO SM
203+         if  (cpuid == 0 ) {
204+             int  off = 0 ;
205+             _ccountPgm = new  PIOProgram (&ccount_program);
206+             _ccountPgm->prepare (&_pio, &_sm, &off);
207+             ccount_program_init (_pio, _sm, off);
208+             pio_sm_set_enabled (_pio, _sm, true );
212209        }
213210#endif 
214211    }
@@ -255,21 +252,17 @@ class RP2040 {
255252        @returns CPU clock cycles since power up 
256253    */  
257254    inline  uint32_t  getCycleCount () {
258- #if  !defined(__riscv) && !defined(__PROFILE)
255+ #if  !defined(__riscv) && !defined(__PROFILE) && !defined(__FREERTOS) 
259256        //  Get CPU cycle count.  Needs to do magic to extend 24b HW to something longer
260-         if  (!__isFreeRTOS) {
261-             uint32_t  epoch;
262-             uint32_t  ctr;
263-             do  {
264-                 epoch = (uint32_t )_epoch[sio_hw->cpuid ];
265-                 ctr = systick_hw->cvr ;
266-             } while  (epoch != (uint32_t )_epoch[sio_hw->cpuid ]);
267-             return  epoch + (1  << 24 ) - ctr; /*  CTR counts down from 1<<24-1 */ 
268-         } else  {
269- #endif
270-             return  ccount_read (_pio, _sm);
271- #if  !defined(__riscv) && !defined(__PROFILE)
272-         }
257+         uint32_t  epoch;
258+         uint32_t  ctr;
259+         do  {
260+             epoch = (uint32_t )_epoch[sio_hw->cpuid ];
261+             ctr = systick_hw->cvr ;
262+         } while  (epoch != (uint32_t )_epoch[sio_hw->cpuid ]);
263+         return  epoch + (1  << 24 ) - ctr; /*  CTR counts down from 1<<24-1 */ 
264+ #else 
265+         return  ccount_read (_pio, _sm);
273266#endif 
274267    }
275268    /* *
@@ -278,20 +271,16 @@ class RP2040 {
278271        @returns CPU clock cycles since power up 
279272    */  
280273    inline  uint64_t  getCycleCount64 () {
281- #if  !defined(__riscv) && !defined(__PROFILE)
282-         if  (!__isFreeRTOS) {
283-             uint64_t  epoch;
284-             uint64_t  ctr;
285-             do  {
286-                 epoch = _epoch[sio_hw->cpuid ];
287-                 ctr = systick_hw->cvr ;
288-             } while  (epoch != _epoch[sio_hw->cpuid ]);
289-             return  epoch + (1LL  << 24 ) - ctr;
290-         } else  {
291- #endif
292-             return  ccount_read (_pio, _sm);
293- #if  !defined(__riscv) && !defined(__PROFILE)
294-         }
274+ #if  !defined(__riscv) && !defined(__PROFILE) && !defined(__FREERTOS)
275+         uint64_t  epoch;
276+         uint64_t  ctr;
277+         do  {
278+             epoch = _epoch[sio_hw->cpuid ];
279+             ctr = systick_hw->cvr ;
280+         } while  (epoch != _epoch[sio_hw->cpuid ]);
281+         return  epoch + (1LL  << 24 ) - ctr;
282+ #else 
283+         return  ccount_read (_pio, _sm);
295284#endif 
296285    }
297286
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