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Add support for RP2350
1 parent f0cbc0a commit 975560a

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+43
-8
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1 file changed

+43
-8
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cores/rp2040/RP2040Support.h

Lines changed: 43 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,11 @@
2222
#include <hardware/irq.h>
2323
#include <hardware/pio.h>
2424
#include <pico/unique_id.h>
25+
#ifdef PICO_RP2350
26+
#include <hardware/regs/powman.h>
27+
#else
2528
#include <hardware/regs/vreg_and_chip_reset.h>
29+
#endif
2630
#include <hardware/exception.h>
2731
#include <hardware/watchdog.h>
2832
#include <hardware/structs/rosc.h>
@@ -353,27 +357,58 @@ class RP2040 {
353357
watchdog_update();
354358
}
355359

356-
enum resetReason_t {UNKNOWN_RESET, PWRON_RESET, RUN_PIN_RESET, SOFT_RESET, WDT_RESET, DEBUG_RESET};
360+
enum resetReason_t {UNKNOWN_RESET, PWRON_RESET, RUN_PIN_RESET, SOFT_RESET, WDT_RESET, DEBUG_RESET, GLITCH_RESET, BROWNOUT_RESET};
357361

358362
resetReason_t getResetReason(void) {
359363
io_rw_32 *WD_reason_reg = (io_rw_32 *)(WATCHDOG_BASE + WATCHDOG_REASON_OFFSET);
360-
io_rw_32 *rrp = (io_rw_32 *)(VREG_AND_CHIP_RESET_BASE + VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET);
361364

362-
if (watchdog_caused_reboot() && watchdog_enable_caused_reboot()) // watchdog timer
365+
if (watchdog_caused_reboot() && watchdog_enable_caused_reboot()) { // watchdog timer
363366
return WDT_RESET;
367+
}
364368

365-
if (*WD_reason_reg & WATCHDOG_REASON_TIMER_BITS) // soft reset() or reboot()
369+
if (*WD_reason_reg & WATCHDOG_REASON_TIMER_BITS) { // soft reset() or reboot()
366370
return SOFT_RESET;
371+
}
372+
373+
#ifdef PICO_RP2350
374+
// **** RP2350 is untested ****
375+
io_rw_32 *rrp = (io_rw_32 *)(POWMAN_BASE + POWMAN_CHIP_RESET_OFFSET);
367376

368-
if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS) // POR: power-on reset or brown-out detection
377+
if (*rrp & POWMAN_CHIP_RESET_HAD_POR_BITS) { // POR: power-on reset (brownout is separately detected on RP2350)
369378
return PWRON_RESET;
379+
}
370380

371-
if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS) // RUN pin
381+
if (*rrp & POWMAN_CHIP_RESET_HAD_RUN_LOW_BITS) { // RUN pin
372382
return RUN_PIN_RESET;
383+
}
373384

374-
if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS) // DEBUG port
375-
return DEBUG_RESET; // **** untested **** debug reset may just cause a rebootToBootloader()
385+
if ((*rrp & POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_BITS) || (*rrp & POWMAN_CHIP_RESET_HAD_RESCUE_BITS) || (*rrp & POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_BITS)) { // DEBUG port
386+
return DEBUG_RESET;
387+
}
388+
389+
if (*rrp & POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_BITS) { // power supply glitch
390+
return GLITCH_RESET;
391+
}
376392

393+
if (*rrp & POWMAN_CHIP_RESET_HAD_BOR_BITS) { // power supply brownout reset
394+
return BROWNOUT_RESET;
395+
}
396+
397+
#else
398+
io_rw_32 *rrp = (io_rw_32 *)(VREG_AND_CHIP_RESET_BASE + VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET);
399+
400+
if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS) { // POR: power-on reset or brown-out detection
401+
return PWRON_RESET;
402+
}
403+
404+
if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS) { // RUN pin
405+
return RUN_PIN_RESET;
406+
}
407+
408+
if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS) { // DEBUG port
409+
return DEBUG_RESET; // **** untested **** debug reset may just cause a rebootToBootloader()
410+
}
411+
#endif
377412
return UNKNOWN_RESET;
378413
}
379414

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