diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp
index 05993a277..3eb9fc461 100644
--- a/libraries/SPI/src/SPI.cpp
+++ b/libraries/SPI/src/SPI.cpp
@@ -179,6 +179,12 @@ void SPIClassRP2040::transfer(const void *txbuf, void *rxbuf, size_t count) {
     DEBUGSPI("SPI::transfer completed\n");
 }
 
+#ifdef PICO_RP2350B
+#define GPIOIRQREGS 6
+#else
+#define GPIOIRQREGS 4
+#endif
+
 void SPIClassRP2040::beginTransaction(SPISettings settings) {
     noInterrupts(); // Avoid possible race conditions if IRQ comes in while main app is in middle of this
     DEBUGSPI("SPI::beginTransaction(clk=%lu, bo=%s)\n", settings.getClockFreq(), (settings.getBitOrder() == MSBFIRST) ? "MSB" : "LSB");
@@ -201,7 +207,7 @@ void SPIClassRP2040::beginTransaction(SPISettings settings) {
     }
     // Disable any IRQs that are being used for SPI
     io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
-    DEBUGSPI("SPI: IRQ masks before = %08x %08x %08x %08x\n", (unsigned)irq_ctrl_base->inte[0], (unsigned)irq_ctrl_base->inte[1], (unsigned)irq_ctrl_base->inte[2], (unsigned)irq_ctrl_base->inte[3]);
+    DEBUGSPI("SPI: IRQ masks before = %08x %08x %08x %08x %08x %08x\n", (unsigned)irq_ctrl_base->inte[0], (unsigned)irq_ctrl_base->inte[1], (unsigned)irq_ctrl_base->inte[2], (unsigned)irq_ctrl_base->inte[3], (GPIOIRQREGS > 4) ? (unsigned)irq_ctrl_base->inte[4] : 0, (GPIOIRQREGS > 5) ? (unsigned)irq_ctrl_base->inte[5] : 0);
     for (auto entry : _usingIRQs) {
         int gpio = entry.first;
 
@@ -212,7 +218,7 @@ void SPIClassRP2040::beginTransaction(SPISettings settings) {
         DEBUGSPI("SPI: GPIO %d = %lu\n", gpio, val);
         (*en_reg) ^= val << (4 * (gpio % 8));
     }
-    DEBUGSPI("SPI: IRQ masks after = %08x %08x %08x %08x\n", (unsigned)irq_ctrl_base->inte[0], (unsigned)irq_ctrl_base->inte[1], (unsigned)irq_ctrl_base->inte[2], (unsigned)irq_ctrl_base->inte[3]);
+    DEBUGSPI("SPI: IRQ masks after = %08x %08x %08x %08x %08x %08x\n", (unsigned)irq_ctrl_base->inte[0], (unsigned)irq_ctrl_base->inte[1], (unsigned)irq_ctrl_base->inte[2], (unsigned)irq_ctrl_base->inte[3], (GPIOIRQREGS > 4) ? (unsigned)irq_ctrl_base->inte[4] : 0, (GPIOIRQREGS > 5) ? (unsigned)irq_ctrl_base->inte[5] : 0);
     interrupts();
 }
 
@@ -227,7 +233,7 @@ void SPIClassRP2040::endTransaction(void) {
     }
     io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
     (void) irq_ctrl_base;
-    DEBUGSPI("SPI: IRQ masks = %08x %08x %08x %08x\n", (unsigned)irq_ctrl_base->inte[0], (unsigned)irq_ctrl_base->inte[1], (unsigned)irq_ctrl_base->inte[2], (unsigned)irq_ctrl_base->inte[3]);
+    DEBUGSPI("SPI: IRQ masks = %08x %08x %08x %08x %08x %08x\n", (unsigned)irq_ctrl_base->inte[0], (unsigned)irq_ctrl_base->inte[1], (unsigned)irq_ctrl_base->inte[2], (unsigned)irq_ctrl_base->inte[3], (GPIOIRQREGS > 4) ? (unsigned)irq_ctrl_base->inte[4] : 0, (GPIOIRQREGS > 5) ? (unsigned)irq_ctrl_base->inte[5] : 0);
     interrupts();
 }
 
diff --git a/libraries/lwIP_Ethernet/src/LwipEthernet.cpp b/libraries/lwIP_Ethernet/src/LwipEthernet.cpp
index a9cc60e7f..7a8adedfc 100644
--- a/libraries/lwIP_Ethernet/src/LwipEthernet.cpp
+++ b/libraries/lwIP_Ethernet/src/LwipEthernet.cpp
@@ -75,14 +75,22 @@ void __removeEthernetPacketHandler(int id) {
 }
 
 #define GPIOSTACKSIZE 8
-static uint32_t gpioMaskStack[GPIOSTACKSIZE][4];
-static uint32_t gpioMask[4] = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff};
+#ifdef PICO_RP2350B
+#define GPIOIRQREGS 6
+#define GPIOIRQREGSINIT 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+#else
+#define GPIOIRQREGS 4
+#define GPIOIRQREGSINIT 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+#endif
+
+static uint32_t gpioMaskStack[GPIOSTACKSIZE][GPIOIRQREGS];
+static uint32_t gpioMask[GPIOIRQREGS] = {GPIOIRQREGSINIT};
 
 void ethernet_arch_lwip_gpio_mask() {
     noInterrupts();
-    memmove(gpioMaskStack[1], gpioMaskStack[0], 4 * sizeof(uint32_t) * (GPIOSTACKSIZE - 1)); // Push down the stack
+    memmove(gpioMaskStack[1], gpioMaskStack[0], GPIOIRQREGS * sizeof(uint32_t) * (GPIOSTACKSIZE - 1)); // Push down the stack
     io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl;
-    for (int i = 0; i < 4; i++) {
+    for (int i = 0; i < GPIOIRQREGS; i++) {
         gpioMaskStack[0][i] = irq_ctrl_base->inte[i];
         irq_ctrl_base->inte[i] = irq_ctrl_base->inte[i] & gpioMask[i];
     }
@@ -92,10 +100,10 @@ void ethernet_arch_lwip_gpio_mask() {
 void ethernet_arch_lwip_gpio_unmask() {
     noInterrupts();
     io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl;
-    for (int i = 0; i < 4; i++) {
+    for (int i = 0; i < GPIOIRQREGS; i++) {
         irq_ctrl_base->inte[i] = gpioMaskStack[0][i];
     }
-    memmove(gpioMaskStack[0], gpioMaskStack[1],  4 * sizeof(uint32_t) * (GPIOSTACKSIZE - 1)); // Pop up the stack
+    memmove(gpioMaskStack[0], gpioMaskStack[1],  GPIOIRQREGS * sizeof(uint32_t) * (GPIOSTACKSIZE - 1)); // Pop up the stack
     interrupts();
 }