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Uses an external BCLK and LRCLK to control timing of the I2S data output. Useful for synchronizing to an external device or for higher precision clocking than the internal PLL can provide.

Uses an external BCLK and LRCLK to control timing of the I2S data output.
Useful for synchronizing to an external device or for higher precision
clocking than the internal PLL can provide.
Don't block on a PULL, just send the X register out (will be set to
0 by the setup code).
@earlephilhower earlephilhower merged commit 41ee45c into master Sep 30, 2025
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@earlephilhower earlephilhower deleted the sla branch September 30, 2025 20:18
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2 participants