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| 1 | +.. |
| 2 | + # ******************************************************************************* |
| 3 | + # Copyright (c) 2025 Contributors to the Eclipse Foundation |
| 4 | + # |
| 5 | + # See the NOTICE file(s) distributed with this work for additional |
| 6 | + # information regarding copyright ownership. |
| 7 | + # |
| 8 | + # This program and the accompanying materials are made available under the |
| 9 | + # terms of the Apache License Version 2.0 which is available at |
| 10 | + # https://www.apache.org/licenses/LICENSE-2.0 |
| 11 | + # |
| 12 | + # SPDX-License-Identifier: Apache-2.0 |
| 13 | + # ******************************************************************************* |
| 14 | +
|
| 15 | +Rust Containers Architecture |
| 16 | +============================ |
| 17 | + |
| 18 | +.. document:: Rust Containers Architecture |
| 19 | + :id: doc__containers_rust_architecture |
| 20 | + :status: draft |
| 21 | + :safety: ASIL_B |
| 22 | + :security: NO |
| 23 | + :realizes: wp__component_arch |
| 24 | + :tags: baselibs_rust_containers_rust |
| 25 | + |
| 26 | + |
| 27 | +Overview |
| 28 | +-------- |
| 29 | + |
| 30 | +The implementation of the containers library comprises two main parts: |
| 31 | + |
| 32 | +- The generic storage abstraction for elements, with two concrete implementations: |
| 33 | + heap-allocated and inline storage |
| 34 | +- The generic logic for each container type, each of which has two specializations: |
| 35 | + one using heap-allocated storage, and one using inline storage |
| 36 | + |
| 37 | +Static Architecture |
| 38 | +------------------- |
| 39 | + |
| 40 | +.. comp_arc_sta:: Rust Containers |
| 41 | + :id: comp_arc_sta__baselibs_rust__containers_rust |
| 42 | + :security: YES |
| 43 | + :safety: ASIL_B |
| 44 | + :status: valid |
| 45 | + :tags: baselibs_rust_containers_rust |
| 46 | + :implements: logic_arc_int__b_r__fixvec, logic_arc_int__b_r__inlinevec, logic_arc_int__b_r__fixqueue, logic_arc_int__b_r__inlqueue |
| 47 | + |
| 48 | + .. needarch:: |
| 49 | + :scale: 50 |
| 50 | + :align: center |
| 51 | + |
| 52 | + {{ draw_component(need(), needs) }} |
| 53 | + |
| 54 | + |
| 55 | +Interfaces |
| 56 | +---------- |
| 57 | + |
| 58 | +.. logic_arc_int:: Fixed-Capacity Vector |
| 59 | + :id: logic_arc_int__b_r__fixvec |
| 60 | + :security: YES |
| 61 | + :safety: ASIL_B |
| 62 | + :status: valid |
| 63 | + |
| 64 | +.. logic_arc_int_op:: Push |
| 65 | + :id: logic_arc_int_op__cont__fixvec_push |
| 66 | + :security: YES |
| 67 | + :safety: ASIL_B |
| 68 | + :status: valid |
| 69 | + :included_by: logic_arc_int__b_r__fixvec |
| 70 | + |
| 71 | +.. logic_arc_int_op:: Pop |
| 72 | + :id: logic_arc_int_op__cont__fixvec_pop |
| 73 | + :security: YES |
| 74 | + :safety: ASIL_B |
| 75 | + :status: valid |
| 76 | + :included_by: logic_arc_int__b_r__fixvec |
| 77 | + |
| 78 | +.. logic_arc_int_op:: Clear |
| 79 | + :id: logic_arc_int_op__cont__fixvec_clear |
| 80 | + :security: YES |
| 81 | + :safety: ASIL_B |
| 82 | + :status: valid |
| 83 | + :included_by: logic_arc_int__b_r__fixvec |
| 84 | + |
| 85 | +.. logic_arc_int_op:: Index |
| 86 | + :id: logic_arc_int_op__cont__fixvec_index |
| 87 | + :security: YES |
| 88 | + :safety: ASIL_B |
| 89 | + :status: valid |
| 90 | + :included_by: logic_arc_int__b_r__fixvec |
| 91 | + |
| 92 | +.. logic_arc_int_op:: Iterate |
| 93 | + :id: logic_arc_int_op__cont__fixvec_iterate |
| 94 | + :security: YES |
| 95 | + :safety: ASIL_B |
| 96 | + :status: valid |
| 97 | + :included_by: logic_arc_int__b_r__fixvec |
| 98 | + |
| 99 | + |
| 100 | +.. logic_arc_int:: Inline-Storage Vector |
| 101 | + :id: logic_arc_int__b_r__inlinevec |
| 102 | + :security: YES |
| 103 | + :safety: ASIL_B |
| 104 | + :status: valid |
| 105 | + |
| 106 | +.. logic_arc_int_op:: Push |
| 107 | + :id: logic_arc_int_op__cont__inlinevec_push |
| 108 | + :security: YES |
| 109 | + :safety: ASIL_B |
| 110 | + :status: valid |
| 111 | + :included_by: logic_arc_int__b_r__inlinevec |
| 112 | + |
| 113 | +.. logic_arc_int_op:: Pop |
| 114 | + :id: logic_arc_int_op__cont__inlinevec_pop |
| 115 | + :security: YES |
| 116 | + :safety: ASIL_B |
| 117 | + :status: valid |
| 118 | + :included_by: logic_arc_int__b_r__inlinevec |
| 119 | + |
| 120 | +.. logic_arc_int_op:: Clear |
| 121 | + :id: logic_arc_int_op__cont__inlinevec_clear |
| 122 | + :security: YES |
| 123 | + :safety: ASIL_B |
| 124 | + :status: valid |
| 125 | + :included_by: logic_arc_int__b_r__inlinevec |
| 126 | + |
| 127 | +.. logic_arc_int_op:: Index |
| 128 | + :id: logic_arc_int_op__cont__inlinevec_index |
| 129 | + :security: YES |
| 130 | + :safety: ASIL_B |
| 131 | + :status: valid |
| 132 | + :included_by: logic_arc_int__b_r__inlinevec |
| 133 | + |
| 134 | +.. logic_arc_int_op:: Iterate |
| 135 | + :id: logic_arc_int_op__cont__inlinevec_iterate |
| 136 | + :security: YES |
| 137 | + :safety: ASIL_B |
| 138 | + :status: valid |
| 139 | + :included_by: logic_arc_int__b_r__inlinevec |
| 140 | + |
| 141 | + |
| 142 | +.. logic_arc_int:: Fixed-Capacity Queue |
| 143 | + :id: logic_arc_int__b_r__fixqueue |
| 144 | + :security: YES |
| 145 | + :safety: ASIL_B |
| 146 | + :status: valid |
| 147 | + |
| 148 | +.. logic_arc_int_op:: Push Front |
| 149 | + :id: logic_arc_int_op__cont__fixqueue_pushfront |
| 150 | + :security: YES |
| 151 | + :safety: ASIL_B |
| 152 | + :status: valid |
| 153 | + :included_by: logic_arc_int__b_r__fixqueue |
| 154 | + |
| 155 | +.. logic_arc_int_op:: Push Back |
| 156 | + :id: logic_arc_int_op__cont__fixqueue_pushback |
| 157 | + :security: YES |
| 158 | + :safety: ASIL_B |
| 159 | + :status: valid |
| 160 | + :included_by: logic_arc_int__b_r__fixqueue |
| 161 | + |
| 162 | +.. logic_arc_int_op:: Pop Front |
| 163 | + :id: logic_arc_int_op__cont__fixqueue_popfront |
| 164 | + :security: YES |
| 165 | + :safety: ASIL_B |
| 166 | + :status: valid |
| 167 | + :included_by: logic_arc_int__b_r__fixqueue |
| 168 | + |
| 169 | +.. logic_arc_int_op:: Pop Back |
| 170 | + :id: logic_arc_int_op__cont__fixqueue_popback |
| 171 | + :security: YES |
| 172 | + :safety: ASIL_B |
| 173 | + :status: valid |
| 174 | + :included_by: logic_arc_int__b_r__fixqueue |
| 175 | + |
| 176 | +.. logic_arc_int_op:: Clear |
| 177 | + :id: logic_arc_int_op__cont__fixqueue_clear |
| 178 | + :security: YES |
| 179 | + :safety: ASIL_B |
| 180 | + :status: valid |
| 181 | + :included_by: logic_arc_int__b_r__fixqueue |
| 182 | + |
| 183 | +.. logic_arc_int_op:: Iterate |
| 184 | + :id: logic_arc_int_op__cont__fixqueue_iterate |
| 185 | + :security: YES |
| 186 | + :safety: ASIL_B |
| 187 | + :status: valid |
| 188 | + :included_by: logic_arc_int__b_r__fixqueue |
| 189 | + |
| 190 | + |
| 191 | +.. logic_arc_int:: Inline-Storage Queue |
| 192 | + :id: logic_arc_int__b_r__inlqueue |
| 193 | + :security: YES |
| 194 | + :safety: ASIL_B |
| 195 | + :status: valid |
| 196 | + |
| 197 | +.. logic_arc_int_op:: Push Front |
| 198 | + :id: logic_arc_int_op__cont__inlqueue_pushfront |
| 199 | + :security: YES |
| 200 | + :safety: ASIL_B |
| 201 | + :status: valid |
| 202 | + :included_by: logic_arc_int__b_r__inlqueue |
| 203 | + |
| 204 | +.. logic_arc_int_op:: Push Back |
| 205 | + :id: logic_arc_int_op__cont__inlqueue_pushback |
| 206 | + :security: YES |
| 207 | + :safety: ASIL_B |
| 208 | + :status: valid |
| 209 | + :included_by: logic_arc_int__b_r__inlqueue |
| 210 | + |
| 211 | +.. logic_arc_int_op:: Pop Front |
| 212 | + :id: logic_arc_int_op__cont__inlqueue_popfront |
| 213 | + :security: YES |
| 214 | + :safety: ASIL_B |
| 215 | + :status: valid |
| 216 | + :included_by: logic_arc_int__b_r__inlqueue |
| 217 | + |
| 218 | +.. logic_arc_int_op:: Pop Back |
| 219 | + :id: logic_arc_int_op__cont__inlqueue_popback |
| 220 | + :security: YES |
| 221 | + :safety: ASIL_B |
| 222 | + :status: valid |
| 223 | + :included_by: logic_arc_int__b_r__inlqueue |
| 224 | + |
| 225 | +.. logic_arc_int_op:: Clear |
| 226 | + :id: logic_arc_int_op__cont__inlqueue_clear |
| 227 | + :security: YES |
| 228 | + :safety: ASIL_B |
| 229 | + :status: valid |
| 230 | + :included_by: logic_arc_int__b_r__inlqueue |
| 231 | + |
| 232 | +.. logic_arc_int_op:: Iterate |
| 233 | + :id: logic_arc_int_op__cont__inlqueue_iterate |
| 234 | + :security: YES |
| 235 | + :safety: ASIL_B |
| 236 | + :status: valid |
| 237 | + :included_by: logic_arc_int__b_r__inlqueue |
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