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1 parent 9f3e35d commit 39f3c86Copy full SHA for 39f3c86
ports/xtensa/xcc/src/tx_clib_lock.c
@@ -35,6 +35,10 @@
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/* DATE NAME DESCRIPTION */
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/* */
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/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
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+/* 12-31-2023 Xiuwen Cai Modified comment(s), and */
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+/* added error handling in */
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+/* lock initialization, */
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+/* resulting in version 6.4.0 */
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/**************************************************************************/
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@@ -155,6 +159,8 @@ _Mtxinit (_Rmtx * mtx)
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if (lcnt >= XT_NUM_CLIB_LOCKS) {
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/* Fatal error */
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+ *mtx = NULL;
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+ return;
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}
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lock = &(xclib_locks[lcnt]);
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