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Scott Larson
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Add Cortex M55 and M85 to ports
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‎ports/cortex_m55/ac6/CmakeLists.txt

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target_sources(${PROJECT_NAME} PRIVATE
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${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
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${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
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${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack.c
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_allocate.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_free.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
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)
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target_include_directories(${PROJECT_NAME} PUBLIC
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inc
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)

‎ports/cortex_m55/ac6/inc/tx_port.h

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‎ports/cortex_m55/ac6/inc/tx_secure_interface.h

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/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/* */
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/* COMPONENT DEFINITION RELEASE */
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/* */
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/* tx_secure_interface.h PORTABLE C */
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/* 6.1 */
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/* AUTHOR */
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/* */
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/* Scott Larson, Microsoft Corporation */
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/* */
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/* DESCRIPTION */
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/* */
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/* This file defines the ThreadX secure thread stack components, */
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/* including data types and external references. */
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/* It is assumed that tx_api.h and tx_port.h have already been */
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/* included. */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 09-30-2020 Scott Larson Initial Version 6.1 */
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/* */
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/**************************************************************************/
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#ifndef TX_SECURE_INTERFACE_H
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#define TX_SECURE_INTERFACE_H
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/* Define internal secure thread stack function prototypes. */
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extern UINT _tx_thread_secure_mode_stack_initialize(void);
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extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size);
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extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr);
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extern void _tx_thread_secure_stack_initialize(void);
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extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr);
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extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr);
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#endif

‎ports/cortex_m55/ac6/readme_threadx.txt

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Microsoft's Azure RTOS ThreadX for Cortex-M55
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Using the AC6 Tools in Keil uVision
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1. Import the ThreadX Projects
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In order to build the ThreadX library and the ThreadX demonstration, first open
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the AzureRTOS.uvmpw workspace (located in the "example_build" directory)
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into Keil.
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2. Building the ThreadX run-time Library
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Building the ThreadX library is easy; simply set the ThreadX_Library project
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as active, then then build the library. You should now observe the compilation
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and assembly of the ThreadX library. This project build produces the ThreadX
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library file ThreadX_Library.lib.
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Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
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replace the common files of the same name.
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3. Demonstration System
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The ThreadX demonstration is designed to execute under the Keil debugger on the
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FVP_MPS2_Cortex-M55_MDK simulator.
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Building the demonstration is easy; simply select the "Batch Build" button.
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You should now observe the compilation and assembly of the ThreadX demonstration of
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both the demo_secure_zone and demo_threadx_non-secure_zone projects.
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Then click the Start/Stop Debug Session button to start the simulator and begin debugging.
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You are now ready to execute the ThreadX demonstration.
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4. System Initialization
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The entry point in ThreadX for the Cortex-M55 using AC6 tools uses the standard AC6
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Cortex-M55 reset sequence. From the reset vector the C runtime will be initialized.
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The ThreadX tx_initialize_low_level.s file is responsible for setting up
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various system data structures, the vector area, and a periodic timer interrupt
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source.
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In addition, _tx_initialize_low_level determines the first available
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address for use by the application, which is supplied as the sole input
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parameter to your application definition function, tx_application_define.
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5. Register Usage and Stack Frames
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The following defines the saved context stack frames for context switches
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that occur as a result of interrupt handling or from thread-level API calls.
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All suspended threads have the same stack frame in the Cortex-M55 version of
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ThreadX. The top of the suspended thread's stack is pointed to by
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tx_thread_stack_ptr in the associated thread control block TX_THREAD.
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Non-FPU Stack Frame:
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Stack Offset Stack Contents
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 r4 Software stacked GP registers
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0x08 r5
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0x0C r6
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0x10 r7
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0x14 r8
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0x18 r9
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0x1C r10
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0x20 r11
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0x24 r0 Hardware stacked registers
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0x28 r1
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0x2C r2
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0x30 r3
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0x34 r12
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0x38 lr
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0x3C pc
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0x40 xPSR
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FPU Stack Frame (only interrupted thread with FPU enabled):
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Stack Offset Stack Contents
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 s16 Software stacked FPU registers
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0x08 s17
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0x0C s18
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0x10 s19
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0x14 s20
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0x18 s21
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0x1C s22
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0x20 s23
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0x24 s24
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0x28 s25
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0x2C s26
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0x30 s27
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0x34 s28
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0x38 s29
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0x3C s30
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0x40 s31
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0x44 r4 Software stacked registers
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0x48 r5
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0x4C r6
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0x50 r7
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0x54 r8
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0x58 r9
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0x5C r10
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0x60 r11
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0x64 r0 Hardware stacked registers
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0x68 r1
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0x6C r2
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0x70 r3
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0x74 r12
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0x78 lr
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0x7C pc
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0x80 xPSR
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0x84 s0 Hardware stacked FPU registers
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0x88 s1
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0x8C s2
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0x90 s3
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0x94 s4
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0x98 s5
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0x9C s6
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0xA0 s7
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0xA4 s8
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0xA8 s9
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0xAC s10
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0xB0 s11
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0xB4 s12
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0xB8 s13
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0xBC s14
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0xC0 s15
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0xC4 fpscr
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6. Improving Performance
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To make ThreadX and the application(s) run faster, you can enable
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all compiler optimizations.
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In addition, you can eliminate the ThreadX basic API error checking by
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compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
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defined.
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7. Interrupt Handling
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ThreadX provides complete and high-performance interrupt handling for Cortex-M55
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targets. There are a certain set of requirements that are defined in the
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following sub-sections:
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7.1 Vector Area
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The Cortex-M55 vectors start at the label __Vectors or similar. The application may modify
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the vector area according to its needs. There is code in tx_initialize_low_level() that will
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configure the vector base register.
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7.2 Managed Interrupts
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ISRs can be written completely in C (or assembly language) without any calls to
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_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the
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ThreadX API that is available to ISRs.
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ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
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void your_C_isr(void)
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{
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/* ISR processing goes here, including any needed function calls. */
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}
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ISRs written in assembly language will take the form:
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.global your_assembly_isr
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.thumb_func
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your_assembly_isr:
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; VOID your_assembly_isr(VOID)
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; {
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PUSH {r0, lr}
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;
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; /* Do interrupt handler work here */
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; /* BL <your interrupt routine in C> */
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POP {r0, lr}
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BX lr
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; }
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Note: the Cortex-M55 requires exception handlers to be thumb labels, this implies bit 0 set.
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To accomplish this, the declaration of the label has to be preceded by the assembler directive
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.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to
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be inserted in the correct location in the interrupt vector table. This table is typically
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located in either your runtime startup file or in the tx_initialize_low_level.s file.
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8. FPU Support
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ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads
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can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread
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context.
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9. Revision History
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For generic code revision information, please refer to the readme_threadx_generic.txt
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file, which is included in your distribution. The following details the revision
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information associated with this specific port of ThreadX:
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06-02-2021 Release 6.1.7 changes:
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tx_port.h Remove unneeded include file
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tx_thread_secure_stack_initialize.S New file
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tx_thread_schedule.S Added secure stack initialize to SVC hander
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tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode
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04-02-2021 Release 6.1.6 changes:
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tx_port.h Updated macro definition
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tx_thread_schedule.s Added low power support
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03-02-2021 The following files were changed/added for version 6.1.5:
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tx_port.h Added ULONG64_DEFINED
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09-30-2020 Initial ThreadX 6.1 version for Cortex-M55 using AC6 tools.
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Copyright(c) 1996-2020 Microsoft Corporation
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https://azure.com/rtos
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