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Added thumb mode support for threadX GNU ports on armv7a platforms. (#333)
* Added thumb mode support for threadX GNU ports on armv7a platforms. https://msazure.visualstudio.com/One/_workitems/edit/26105175/ * move the swi interrupt to tx_initialize_low_level.S. * update the test log.
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‎ports/cortex_a12/ac6/src/tx_thread_context_restore.S

Lines changed: 24 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -23,16 +23,16 @@
2323
#include "tx_user.h"
2424
#endif
2525

26-
.arm
27-
28-
#ifdef TX_ENABLE_FIQ_SUPPORT
29-
SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode
30-
IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode
26+
.syntax unified
27+
#if defined(THUMB_MODE)
28+
.thumb
3129
#else
32-
SVC_MODE = 0x93 // Disable IRQ, SVC mode
33-
IRQ_MODE = 0x92 // Disable IRQ, IRQ mode
30+
.arm
3431
#endif
3532

33+
SVC_MODE = 0x13 // SVC mode
34+
IRQ_MODE = 0x12 // IRQ mode
35+
3636
.global _tx_thread_system_state
3737
.global _tx_thread_current_ptr
3838
.global _tx_thread_execute_ptr
@@ -45,15 +45,14 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode
4545
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore
4646
since it will never be called 16-bit mode. */
4747

48-
.arm
4948
.text
5049
.align 2
5150
/**************************************************************************/
5251
/* */
5352
/* FUNCTION RELEASE */
5453
/* */
5554
/* _tx_thread_context_restore ARMv7-A */
56-
/* 6.3.0 */
55+
/* 6.x */
5756
/* AUTHOR */
5857
/* */
5958
/* William E. Lamie, Microsoft Corporation */
@@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode
9493
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
9594
/* #include tx_user.h, */
9695
/* resulting in version 6.3.0 */
96+
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
97+
/* Added thumb mode support, */
98+
/* resulting in version 6.x */
9799
/* */
98100
/**************************************************************************/
99101
.global _tx_thread_context_restore
@@ -129,9 +131,9 @@ _tx_thread_context_restore:
129131
/* Just recover the saved registers and return to the point of
130132
interrupt. */
131133

132-
LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
134+
POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
133135
MSR SPSR_cxsf, r0 // Put SPSR back
134-
LDMIA sp!, {r0-r3} // Recover r0-r3
136+
POP {r0-r3} // Recover r0-r3
135137
MOVS pc, lr // Return to point of interrupt
136138

137139
__tx_thread_not_nested_restore:
@@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore:
160162
/* Pickup the saved stack pointer. */
161163

162164
/* Recover the saved context and return to the point of interrupt. */
163-
LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
165+
POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
164166
MSR SPSR_cxsf, r0 // Put SPSR back
165-
LDMIA sp!, {r0-r3} // Recover r0-r3
167+
POP {r0-r3} // Recover r0-r3
166168
MOVS pc, lr // Return to point of interrupt
167169

168170
__tx_thread_preempt_restore:
169171

170-
LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers
172+
POP {r3, r10, r12, lr} // Recover temporarily saved registers
171173
MOV r1, lr // Save lr (point of interrupt)
172-
MOV r2, #SVC_MODE // Build SVC mode CPSR
173-
MSR CPSR_c, r2 // Enter SVC mode
174+
CPS #SVC_MODE // Enter SVC mode
174175
STR r1, [sp, #-4]! // Save point of interrupt
175-
STMDB sp!, {r4-r12, lr} // Save upper half of registers
176+
PUSH {r4-r12, lr} // Save upper half of registers
176177
MOV r4, r3 // Save SPSR in r4
177-
MOV r2, #IRQ_MODE // Build IRQ mode CPSR
178-
MSR CPSR_c, r2 // Enter IRQ mode
179-
LDMIA sp!, {r0-r3} // Recover r0-r3
180-
MOV r5, #SVC_MODE // Build SVC mode CPSR
181-
MSR CPSR_c, r5 // Enter SVC mode
182-
STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack
178+
CPS #IRQ_MODE // Enter IRQ mode
179+
POP {r0-r3} // Recover r0-r3
180+
CPS #SVC_MODE // Enter SVC mode
181+
PUSH {r0-r3} // Save r0-r3 on thread's stack
183182

184183
LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr
185184
LDR r0, [r1] // Pickup current thread pointer
@@ -192,13 +191,11 @@ __tx_thread_preempt_restore:
192191
STR r2, [sp, #-4]! // Save FPSCR
193192
VSTMDB sp!, {D16-D31} // Save D16-D31
194193
VSTMDB sp!, {D0-D15} // Save D0-D15
195-
196194
_tx_skip_irq_vfp_save:
197-
198195
#endif
199196

200197
MOV r3, #1 // Build interrupt stack type
201-
STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR
198+
PUSH {r3, r4} // Save interrupt stack type and SPSR
202199
STR sp, [r0, #8] // Save stack pointer in thread control
203200
// block
204201

@@ -223,6 +220,5 @@ __tx_thread_dont_save_ts:
223220
__tx_thread_idle_system_restore:
224221

225222
/* Just return back to the scheduler! */
226-
MOV r0, #SVC_MODE // Build SVC mode CPSR
227-
MSR CPSR_c, r0 // Enter SVC mode
223+
CPS #SVC_MODE // Enter SVC mode
228224
B _tx_thread_schedule // Return to scheduler

‎ports/cortex_a12/ac6/src/tx_thread_context_save.S

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,13 @@
2323
#include "tx_user.h"
2424
#endif
2525

26+
.syntax unified
27+
#if defined(THUMB_MODE)
28+
.thumb
29+
#else
30+
.arm
31+
#endif
32+
2633
.global _tx_thread_system_state
2734
.global _tx_thread_current_ptr
2835
.global __tx_irq_processing_return
@@ -31,15 +38,14 @@
3138
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save
3239
since it will never be called 16-bit mode. */
3340

34-
.arm
3541
.text
3642
.align 2
3743
/**************************************************************************/
3844
/* */
3945
/* FUNCTION RELEASE */
4046
/* */
4147
/* _tx_thread_context_save ARMv7-A */
42-
/* 6.3.0 */
48+
/* 6.x */
4349
/* AUTHOR */
4450
/* */
4551
/* William E. Lamie, Microsoft Corporation */
@@ -79,6 +85,9 @@
7985
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
8086
/* #include tx_user.h, */
8187
/* resulting in version 6.3.0 */
88+
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
89+
/* Added thumb mode support, */
90+
/* resulting in version 6.x */
8291
/* */
8392
/**************************************************************************/
8493
.global _tx_thread_context_save
@@ -90,7 +99,7 @@ _tx_thread_context_save:
9099

91100
/* Check for a nested interrupt condition. */
92101

93-
STMDB sp!, {r0-r3} // Save some working registers
102+
PUSH {r0-r3} // Save some working registers
94103
#ifdef TX_ENABLE_FIQ_SUPPORT
95104
CPSID if // Disable FIQ interrupts
96105
#endif
@@ -101,15 +110,15 @@ _tx_thread_context_save:
101110

102111
/* Nested interrupt condition. */
103112

104-
ADD r2, r2, #1 // Increment the interrupt counter
113+
ADD r2, #1 // Increment the interrupt counter
105114
STR r2, [r3] // Store it back in the variable
106115

107116
/* Save the rest of the scratch registers on the stack and return to the
108117
calling ISR. */
109118

110119
MRS r0, SPSR // Pickup saved SPSR
111-
SUB lr, lr, #4 // Adjust point of interrupt
112-
STMDB sp!, {r0, r10, r12, lr} // Store other registers
120+
SUB lr, #4 // Adjust point of interrupt
121+
PUSH {r0, r10, r12, lr} // Store other registers
113122

114123
/* Return to the ISR. */
115124

@@ -129,7 +138,7 @@ _tx_thread_context_save:
129138
__tx_thread_not_nested_save:
130139

131140
/* Otherwise, not nested, check to see if a thread was running. */
132-
ADD r2, r2, #1 // Increment the interrupt counter
141+
ADD r2, #1 // Increment the interrupt counter
133142
STR r2, [r3] // Store it back in the variable
134143
LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr
135144
LDR r0, [r1] // Pickup current thread pointer
@@ -140,8 +149,8 @@ __tx_thread_not_nested_save:
140149
/* Save minimal context of interrupted thread. */
141150

142151
MRS r2, SPSR // Pickup saved SPSR
143-
SUB lr, lr, #4 // Adjust point of interrupt
144-
STMDB sp!, {r2, r10, r12, lr} // Store other registers
152+
SUB lr, #4 // Adjust point of interrupt
153+
PUSH {r2, r10, r12, lr} // Store other registers
145154

146155
MOV r10, #0 // Clear stack limit
147156

@@ -174,5 +183,5 @@ __tx_thread_idle_system_save:
174183
POP {lr} // Recover ISR lr
175184
#endif
176185

177-
ADD sp, sp, #16 // Recover saved registers
186+
ADD sp, #16 // Recover saved registers
178187
B __tx_irq_processing_return // Continue IRQ processing

‎ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,13 @@
2323
#include "tx_user.h"
2424
#endif
2525

26+
.syntax unified
27+
#if defined(THUMB_MODE)
28+
.thumb
29+
#else
30+
.arm
31+
#endif
32+
2633
#ifdef TX_ENABLE_FIQ_SUPPORT
2734
DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts
2835
#else
@@ -31,19 +38,14 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts
3138
MODE_MASK = 0x1F // Mode mask
3239
FIQ_MODE_BITS = 0x11 // FIQ mode bits
3340

34-
35-
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end
36-
since it will never be called 16-bit mode. */
37-
38-
.arm
3941
.text
4042
.align 2
4143
/**************************************************************************/
4244
/* */
4345
/* FUNCTION RELEASE */
4446
/* */
4547
/* _tx_thread_fiq_nesting_end ARMv7-A */
46-
/* 6.3.0 */
48+
/* 6.x */
4749
/* AUTHOR */
4850
/* */
4951
/* William E. Lamie, Microsoft Corporation */
@@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits
8890
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
8991
/* #include tx_user.h, */
9092
/* resulting in version 6.3.0 */
93+
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
94+
/* Added thumb mode support, */
95+
/* resulting in version 6.x */
9196
/* */
9297
/**************************************************************************/
98+
#if defined(THUMB_MODE)
99+
.thumb_func
100+
#endif
93101
.global _tx_thread_fiq_nesting_end
94102
.type _tx_thread_fiq_nesting_end,function
95103
_tx_thread_fiq_nesting_end:
@@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end:
103111
ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
104112
MSR CPSR_c, r0 // Reenter IRQ mode
105113

106-
#ifdef __THUMB_INTERWORK
107114
BX r3 // Return to caller
108-
#else
109-
MOV pc, r3 // Return to caller
110-
#endif

‎ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -23,23 +23,25 @@
2323
#include "tx_user.h"
2424
#endif
2525

26+
.syntax unified
27+
#if defined(THUMB_MODE)
28+
.thumb
29+
#else
30+
.arm
31+
#endif
32+
2633
FIQ_DISABLE = 0x40 // FIQ disable bit
2734
MODE_MASK = 0x1F // Mode mask
2835
SYS_MODE_BITS = 0x1F // System mode bits
2936

30-
31-
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start
32-
since it will never be called 16-bit mode. */
33-
34-
.arm
3537
.text
3638
.align 2
3739
/**************************************************************************/
3840
/* */
3941
/* FUNCTION RELEASE */
4042
/* */
4143
/* _tx_thread_fiq_nesting_start ARMv7-A */
42-
/* 6.3.0 */
44+
/* 6.x */
4345
/* AUTHOR */
4446
/* */
4547
/* William E. Lamie, Microsoft Corporation */
@@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits
8183
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
8284
/* #include tx_user.h, */
8385
/* resulting in version 6.3.0 */
86+
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
87+
/* Added thumb mode support, */
88+
/* resulting in version 6.x */
8489
/* */
8590
/**************************************************************************/
91+
#if defined(THUMB_MODE)
92+
.thumb_func
93+
#endif
8694
.global _tx_thread_fiq_nesting_start
8795
.type _tx_thread_fiq_nesting_start,function
8896
_tx_thread_fiq_nesting_start:
@@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start:
95103
// and push r1 just to keep 8-byte alignment
96104
BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
97105
MSR CPSR_c, r0 // Enter system mode
98-
#ifdef __THUMB_INTERWORK
99106
BX r3 // Return to caller
100-
#else
101-
MOV pc, r3 // Return to caller
102-
#endif

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