Implement support for RISC-V ISA Extensions

[fdesbiens]

Objective

Expand ThreadX support to handle RISC-V ISA extensions and enable optional features such as vector support where applicable.

Deliverables

• Identify and document supported RISC-V extensions relevant to embedded ThreadX usage (e.g., RV32G, RV64G, compressed C, vector V).
• Update build system to allow selecting ISA extensions via flags (-march, -mabi, etc.).
• Evaluate and integrate RISC-V vector extension support (where it makes sense) in build/test setup.
• Ensure consistency of extension handling across both 32-bit and 64-bit ports.

Tags

Addition, Medium Complexity