diff --git a/README.md b/README.md index 3c7dc2f26..4ca005b1a 100644 --- a/README.md +++ b/README.md @@ -54,6 +54,7 @@ ARM * [Radxa ROCK 5A](../master/docs/radxa_rock_5a.md) * [Radxa ROCK 5B](../master/docs/radxa_rock_5b.md) * [Radxa ZERO3](../master/docs/radxa_zero3.md) +* [Radxa ROCK Pi E](../master/docs/radxa_rock_pi_e.md) * [Rock Pi 4](../master/docs/rockpi4.md) * [Orange Pi Prime](../master/docs/orange_pi_prime.md) diff --git a/api/mraa/gpio.h b/api/mraa/gpio.h index ce48f820c..4ef6aebd4 100644 --- a/api/mraa/gpio.h +++ b/api/mraa/gpio.h @@ -67,6 +67,7 @@ typedef enum { MRAA_GPIOD_ACTIVE_LOW = 4, MRAA_GPIOD_OPEN_DRAIN = 5, MRAA_GPIOD_OPEN_SOURCE = 6, + MRAA_GPIOD_BIAS_DISABLE = 7, } mraa_gpio_mode_t; /** diff --git a/api/mraa/types.h b/api/mraa/types.h index 843f182ee..e048018bc 100644 --- a/api/mraa/types.h +++ b/api/mraa/types.h @@ -79,6 +79,7 @@ typedef enum { MRAA_RADXA_CM5_IO = 34, /**< Radxa CM5 IO */ MRAA_RADXA_ROCK_3A = 35, /**< Radxa ROCK 3 Model A */ MRAA_RADXA_E25 = 36, /**< Radxa E25 */ + MRAA_RADXA_ROCK_PI_E = 37, /**< Radxa ROCK PI E */ // USB platform extenders start at 256 MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -474,6 +475,38 @@ typedef enum { MRAA_ROCKPI4_PIN40 = 40 } mraa_rockpi4_wiring_t; +/** + * Radxa ROCK Pi E GPIO number enum + */ +typedef enum { + MRAA_RADXA_ROCK_PI_E_PIN3 = 3, + MRAA_RADXA_ROCK_PI_E_PIN5 = 5, + MRAA_RADXA_ROCK_PI_E_PIN7 = 7, + MRAA_RADXA_ROCK_PI_E_PIN8 = 8, + MRAA_RADXA_ROCK_PI_E_PIN10 = 10, + MRAA_RADXA_ROCK_PI_E_PIN11 = 11, + MRAA_RADXA_ROCK_PI_E_PIN12 = 12, + MRAA_RADXA_ROCK_PI_E_PIN13 = 13, + MRAA_RADXA_ROCK_PI_E_PIN15 = 15, + MRAA_RADXA_ROCK_PI_E_PIN19 = 19, + MRAA_RADXA_ROCK_PI_E_PIN21 = 21, + MRAA_RADXA_ROCK_PI_E_PIN22 = 22, + MRAA_RADXA_ROCK_PI_E_PIN23 = 23, + MRAA_RADXA_ROCK_PI_E_PIN24 = 24, + MRAA_RADXA_ROCK_PI_E_PIN26 = 26, + MRAA_RADXA_ROCK_PI_E_PIN27 = 27, + MRAA_RADXA_ROCK_PI_E_PIN28 = 28, + MRAA_RADXA_ROCK_PI_E_PIN29 = 29, + MRAA_RADXA_ROCK_PI_E_PIN31 = 31, + MRAA_RADXA_ROCK_PI_E_PIN32 = 32, + MRAA_RADXA_ROCK_PI_E_PIN33 = 33, + MRAA_RADXA_ROCK_PI_E_PIN35 = 35, + MRAA_RADXA_ROCK_PI_E_PIN36 = 36, + MRAA_RADXA_ROCK_PI_E_PIN37 = 37, + MRAA_RADXA_ROCK_PI_E_PIN38 = 38, + MRAA_RADXA_ROCK_PI_E_PIN40 = 40 +} mraa_radxa_rock_pi_e_wiring_t; + /** * Raspberry PI Wiring compatible numbering enum */ diff --git a/api/mraa/types.hpp b/api/mraa/types.hpp index 9ea483efd..c0d589409 100644 --- a/api/mraa/types.hpp +++ b/api/mraa/types.hpp @@ -73,6 +73,7 @@ typedef enum { RADXA_CM5_IO = 34, /**< Radxa CM5 IO */ RADXA_ROCK_3A = 35, /**< Radxa ROCK 3 Model A */ RADXA_E25 = 36, /**< Radxa E25 */ + RADXA_ROCK_PI_E = 37, /**< Radxa ROCK Pi E */ FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -465,6 +466,38 @@ typedef enum { ROCKPI4_PIN40 = 40 } RockPi4Wiring; +/** + * Radxa ROCK PI E GPIO numbering enum + */ +typedef enum { + RADXA_ROCK_PI_E_PIN3 = 3, + RADXA_ROCK_PI_E_PIN5 = 5, + RADXA_ROCK_PI_E_PIN7 = 7, + RADXA_ROCK_PI_E_PIN8 = 8, + RADXA_ROCK_PI_E_PIN10 = 10, + RADXA_ROCK_PI_E_PIN11 = 11, + RADXA_ROCK_PI_E_PIN12 = 12, + RADXA_ROCK_PI_E_PIN13 = 13, + RADXA_ROCK_PI_E_PIN15 = 15, + RADXA_ROCK_PI_E_PIN19 = 19, + RADXA_ROCK_PI_E_PIN21 = 21, + RADXA_ROCK_PI_E_PIN22 = 22, + RADXA_ROCK_PI_E_PIN23 = 23, + RADXA_ROCK_PI_E_PIN24 = 24, + RADXA_ROCK_PI_E_PIN26 = 26, + RADXA_ROCK_PI_E_PIN27 = 27, + RADXA_ROCK_PI_E_PIN28 = 28, + RADXA_ROCK_PI_E_PIN29 = 29, + RADXA_ROCK_PI_E_PIN31 = 31, + RADXA_ROCK_PI_E_PIN32 = 32, + RADXA_ROCK_PI_E_PIN33 = 33, + RADXA_ROCK_PI_E_PIN35 = 35, + RADXA_ROCK_PI_E_PIN36 = 36, + RADXA_ROCK_PI_E_PIN37 = 37, + RADXA_ROCK_PI_E_PIN38 = 38, + RADXA_ROCK_PI_E_PIN40 = 40 +} RadxaRockPiEWiring; + /** * Raspberry PI Wiring compatible numbering enum */ diff --git a/docs/index.java.md b/docs/index.java.md index cb55323bc..d41f6a2ed 100644 --- a/docs/index.java.md +++ b/docs/index.java.md @@ -63,6 +63,7 @@ Specific platform information for supported platforms is documented here: - @ref radxa_rock_5a - @ref radxa_rock_5b - @ref radxa_zero3 +- @ref radxa_rock_pi_e - @ref rockpi4 ## DEBUGGING diff --git a/docs/index.md b/docs/index.md index 4bd01f406..d338261a0 100644 --- a/docs/index.md +++ b/docs/index.md @@ -71,6 +71,7 @@ Specific platform information for supported platforms is documented here: - @ref radxa_rock_5a - @ref radxa_rock_5b - @ref radxa_zero3 +- @ref radxa_rock_pi_e - @ref rockpi4 ## DEBUGGING diff --git a/docs/radxa_rock_pi_e.md b/docs/radxa_rock_pi_e.md new file mode 100644 index 000000000..9cade9b7d --- /dev/null +++ b/docs/radxa_rock_pi_e.md @@ -0,0 +1,47 @@ +Radxa ROCK Pi E {#_Radxa} +==================== + +Radxa ROCK Pi E is a Rockchip RK3288 based single board computer by Radxa. It can run Android or Linux. + +Interface notes +--------------- + +- UART2 is enabled as the default console. +- All UART ports support baud up to 1500000. + +Pin Mapping +----------- + +Radxa ROCK Pi E has a 40-pin expansion header. Each pin is distinguished by the color. + +| Function5| Function4| Function3| Function2| Function1| PIN | PIN | Function1| Function2| Function3| Function4| Function5| +|----------|----------|-----------|-------------|----------|:------|------:|----------|-------------|-----------|------------|------------| +| | | | | 3V3| 1 | 2 | +5.0V| | | | | +| | | | UART1_TXD| GPIO3_A4| 3 | 4 | +5.0V| | | | | +| | | | UART1_RXD| GPIO3_A6| 5 | 6 | GND| | | | | +| | | | | GPIO1_D4| 7 | 8 | GPIO2_A0| UART2_TX_M1| | | | +| | | | | GND| 9 | 10 | GPIO2_A1| UART2_RX_M1| | | | +| | | | | GPIO2_A2| 11 | 12 | GPIO2_C2| | | | | +| | | | | GPIO2_A3| 13 | 14 | GND| | | | | +| | | | | GPIO0_D3| 15 | 16 | USB20DM| | | | | +| | | | | +3.3V| 17 | 18 | USB20DP| | | | | +| | |SPI_TXD_M2 | | GPIO3_A1| 19 | 20 | GND| | | | | +| | |SPI_RXD_M2 | | GPIO3_A2| 21 | 22 |SARADC_IN1| | | | | +| | |SPI_CLK_M2 | | GPIO3_A0| 23 | 24 | GPIO3_B0| |SPI_CSN0_M2| | | +| | | | | GND| 25 | 26 | GPIO2_B4| | | | | +|PWM0 |I2C1_SDA | | | GPIO2_A4| 27 | 28 | GPIO2_A5| | | I2C1_SCL| PWM1| +| | | | | GPIO2_C4| 29 | 30 | GND| | | | | +| | | | | GPIO2_C5| 31 | 32 | GPIO2_C0| | | | | +|PWM2 | | | | GPIO2_A6| 33 | 34 | GND| | | | | +| | | | | GPIO2_C1| 35 | 36 | GPIO2_B7| | | | | +| | | | | GPIO2_C6| 37 | 38 | GPIO2_C3| | | | | +| | | | | GND| 39 | 40 | GPIO2_C7| | | | | + +Supports +-------- + +You can find additional product support in the following channels: + +- [Product Info](https://docs.radxa.com/rockpi/rockpie) +- [Forums](https://forum.radxa.com/c/rockpie) +- [Github](https://github.com/radxa) \ No newline at end of file diff --git a/include/arm/radxa_rock_pi_e.h b/include/arm/radxa_rock_pi_e.h new file mode 100644 index 000000000..776af03be --- /dev/null +++ b/include/arm/radxa_rock_pi_e.h @@ -0,0 +1,30 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mraa_internal.h" + +#define MRAA_RADXA_ROCK_PI_E_GPIO_COUNT 28 +#define MRAA_RADXA_ROCK_PI_E_I2C_COUNT 1 +#define MRAA_RADXA_ROCK_PI_E_SPI_COUNT 1 +#define MRAA_RADXA_ROCK_PI_E_UART_COUNT 2 +#define MRAA_RADXA_ROCK_PI_E_PWM_COUNT 1 +#define MRAA_RADXA_ROCK_PI_E_AIO_COUNT 1 +#define MRAA_RADXA_ROCK_PI_E_PIN_COUNT 40 +#define PLATFORM_NAME_RADXA_ROCK_PI_E "Radxa ROCK Pi E" + +mraa_board_t * + mraa_radxa_rock_pi_e(); + +#ifdef __cplusplus +} +#endif diff --git a/include/gpio/gpio_chardev.h b/include/gpio/gpio_chardev.h index 5f018ae52..7ddf9b683 100644 --- a/include/gpio/gpio_chardev.h +++ b/include/gpio/gpio_chardev.h @@ -46,6 +46,9 @@ mraa_boolean_t mraa_is_gpio_line_dir_out(mraa_gpiod_line_info *linfo); mraa_boolean_t mraa_is_gpio_line_active_low(mraa_gpiod_line_info *linfo); mraa_boolean_t mraa_is_gpio_line_open_drain(mraa_gpiod_line_info *linfo); mraa_boolean_t mraa_is_gpio_line_open_source(mraa_gpiod_line_info *linfo); +mraa_boolean_t mraa_is_gpio_line_bias_pull_up(mraa_gpiod_line_info *linfo); +mraa_boolean_t mraa_is_gpio_line_bias_pull_down(mraa_gpiod_line_info *linfo); +mraa_boolean_t mraa_is_gpio_line_bias_disable(mraa_gpiod_line_info *linfo); int mraa_get_number_of_gpio_chips(); int mraa_get_chip_infos(mraa_gpiod_chip_info*** cinfos); diff --git a/include/linux/gpio.h b/include/linux/gpio.h index 8451032c6..cb5ad75b9 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -21,6 +21,9 @@ struct gpiochip_info { #define GPIOLINE_FLAG_ACTIVE_LOW (1UL << 2) #define GPIOLINE_FLAG_OPEN_DRAIN (1UL << 3) #define GPIOLINE_FLAG_OPEN_SOURCE (1UL << 4) +#define GPIOLINE_FLAG_BIAS_PULL_UP (1UL << 5) +#define GPIOLINE_FLAG_BIAS_PULL_DOWN (1UL << 6) +#define GPIOLINE_FLAG_BIAS_DISABLE (1UL << 7) struct gpioline_info { __u32 line_offset; @@ -36,6 +39,9 @@ struct gpioline_info { #define GPIOHANDLE_REQUEST_ACTIVE_LOW (1UL << 2) #define GPIOHANDLE_REQUEST_OPEN_DRAIN (1UL << 3) #define GPIOHANDLE_REQUEST_OPEN_SOURCE (1UL << 4) +#define GPIOHANDLE_REQUEST_BIAS_PULL_UP (1UL << 5) +#define GPIOHANDLE_REQUEST_BIAS_PULL_DOWN (1UL << 6) +#define GPIOHANDLE_REQUEST_BIAS_DISABLE (1UL << 7) struct gpiohandle_request { __u32 lineoffsets[GPIOHANDLES_MAX]; diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 10a1d9411..735aca222 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -114,6 +114,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/arm/radxa_e25.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5b.c + ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_pi_e.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_cm5_io.c ${PROJECT_SOURCE_DIR}/src/arm/rockpi4.c ${PROJECT_SOURCE_DIR}/src/arm/adlink_ipi.c diff --git a/src/arm/arm.c b/src/arm/arm.c index 093021006..64b9243f4 100644 --- a/src/arm/arm.c +++ b/src/arm/arm.c @@ -17,6 +17,7 @@ #include "arm/radxa_rock_3c.h" #include "arm/radxa_rock_5a.h" #include "arm/radxa_rock_5b.h" +#include "arm/radxa_rock_pi_e.h" #include "arm/radxa_cm5_io.h" #include "arm/rockpi4.h" #include "arm/de_nano_soc.h" @@ -119,6 +120,8 @@ mraa_arm_platform() platform_type = MRAA_RADXA_ROCK_5B; else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM5_IO)) platform_type = MRAA_RADXA_CM5_IO; + else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_PI_E)) + platform_type = MRAA_RADXA_ROCK_PI_E; else if (mraa_file_contains("/proc/device-tree/model", "ROCK Pi 4") || mraa_file_contains("/proc/device-tree/model", "ROCK PI 4") || mraa_file_contains("/proc/device-tree/model", "ROCK 4") @@ -171,6 +174,9 @@ mraa_arm_platform() case MRAA_RADXA_ROCK_5B: plat = mraa_radxa_rock_5b(); break; + case MRAA_RADXA_ROCK_PI_E: + plat = mraa_radxa_rock_pi_e(); + break; case MRAA_RADXA_CM5_IO: plat = mraa_radxa_cm5_io(); break; diff --git a/src/arm/radxa_rock_pi_e.c b/src/arm/radxa_rock_pi_e.c new file mode 100644 index 000000000..fdf3f127a --- /dev/null +++ b/src/arm/radxa_rock_pi_e.c @@ -0,0 +1,137 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#include +#include +#include +#include +#include +#include "arm/radxa_rock_pi_e.h" +#include "common.h" + +const char* radxa_rock_pi_e_serialdev[MRAA_RADXA_ROCK_PI_E_UART_COUNT] = { "/dev/ttyS1", "/dev/ttyS2"}; + +void +mraa_radxa_rock_pi_e_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name) +{ + + if (index > board->phy_pin_count) + return; + + mraa_pininfo_t* pininfo = &board->pins[index]; + strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE); + + if(pincapabilities_t.gpio == 1) { + pininfo->gpio.gpio_chip = gpio_chip; + pininfo->gpio.gpio_line = gpio_line; + } + + pininfo->capabilities = pincapabilities_t; + + pininfo->gpio.mux_total = 0; +} + +mraa_board_t* +mraa_radxa_rock_pi_e() +{ + mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t)); + if (b == NULL) { + return NULL; + } + + b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t)); + if (b->adv_func == NULL) { + free(b); + return NULL; + } + + // pin mux for buses are setup by default by kernel so tell mraa to ignore them + b->no_bus_mux = 1; + b->phy_pin_count = MRAA_RADXA_ROCK_PI_E_PIN_COUNT + 1; + + b->platform_name = PLATFORM_NAME_RADXA_ROCK_PI_E; + b->chardev_capable = 1; + + // UART + b->uart_dev_count = MRAA_RADXA_ROCK_PI_E_UART_COUNT; + b->def_uart_dev = 0; + b->uart_dev[0].index = 1; + b->uart_dev[1].index = 2; + b->uart_dev[0].device_path = (char*) radxa_rock_pi_e_serialdev[0]; + b->uart_dev[1].device_path = (char*) radxa_rock_pi_e_serialdev[1]; + + // I2C + b->i2c_bus_count = MRAA_RADXA_ROCK_PI_E_I2C_COUNT; + b->def_i2c_bus = 0; + b->i2c_bus[0].bus_id = 1; + + // SPI + b->spi_bus_count = MRAA_RADXA_ROCK_PI_E_SPI_COUNT; + b->def_spi_bus = 0; + b->spi_bus[0].bus_id = 3; + + // PWM + b->pwm_dev_count = MRAA_RADXA_ROCK_PI_E_PWM_COUNT; + b->pwm_default_period = 500; + b->pwm_max_period = 2147483; + b->pwm_min_period = 1; + + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); + if (b->pins == NULL) { + free(b->adv_func); + free(b); + return NULL; + } + + b->pins[33].pwm.parent_id = 2; // pwm2 + b->pins[33].pwm.mux_total = 0; + + // hardware V3.0 + mraa_radxa_rock_pi_e_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID"); + mraa_radxa_rock_pi_e_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_rock_pi_e_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_rock_pi_e_pininfo(b, 3, 3, 4, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO3_A4"); + mraa_radxa_rock_pi_e_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_rock_pi_e_pininfo(b, 5, 3, 6, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO3_A6"); + mraa_radxa_rock_pi_e_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 7, 1, 28, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO1_D4"); + mraa_radxa_rock_pi_e_pininfo(b, 8, 2, 0, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO2_A0"); + mraa_radxa_rock_pi_e_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 10, 2, 1, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO2_A1"); + mraa_radxa_rock_pi_e_pininfo(b, 11, 2, 2, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_A2"); + mraa_radxa_rock_pi_e_pininfo(b, 12, 2, 18, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C2"); + mraa_radxa_rock_pi_e_pininfo(b, 13, 2, 3, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GPIO2_A3"); // Hardware cannot output low level + mraa_radxa_rock_pi_e_pininfo(b, 14, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 15, 0, 27, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO0_D3"); + mraa_radxa_rock_pi_e_pininfo(b, 16, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "USB20DM"); + mraa_radxa_rock_pi_e_pininfo(b, 17, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_rock_pi_e_pininfo(b, 18, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "USB20DP"); + mraa_radxa_rock_pi_e_pininfo(b, 19, 3, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_A1"); + mraa_radxa_rock_pi_e_pininfo(b, 20, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 21, 3, 2, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_A2"); + mraa_radxa_rock_pi_e_pininfo(b, 22, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "SARADC_IN1"); + mraa_radxa_rock_pi_e_pininfo(b, 23, 3, 0, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_A0"); + mraa_radxa_rock_pi_e_pininfo(b, 24, 3, 8, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_B0"); + mraa_radxa_rock_pi_e_pininfo(b, 25, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 26, 2, 12, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_B4"); + mraa_radxa_rock_pi_e_pininfo(b, 27, 2, 4, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO2_A4"); + mraa_radxa_rock_pi_e_pininfo(b, 28, 2, 5, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO2_A5"); + mraa_radxa_rock_pi_e_pininfo(b, 29, 2, 20, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C4"); + mraa_radxa_rock_pi_e_pininfo(b, 30, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 31, 2, 21, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C5"); + mraa_radxa_rock_pi_e_pininfo(b, 32, 2, 16, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C0"); + mraa_radxa_rock_pi_e_pininfo(b, 33, 2, 6, (mraa_pincapabilities_t){1,0,1,0,0,0,0,0}, "GPIO2_A6"); // tied to an IRQ + mraa_radxa_rock_pi_e_pininfo(b, 34, -1, -1,(mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 35, 2, 17, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C1"); + mraa_radxa_rock_pi_e_pininfo(b, 36, 2, 15, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_B7"); + mraa_radxa_rock_pi_e_pininfo(b, 37, 2, 22, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C6"); + mraa_radxa_rock_pi_e_pininfo(b, 38, 2, 19, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C3"); + mraa_radxa_rock_pi_e_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_pi_e_pininfo(b, 40, 2, 23, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_C7"); + + return b; +} diff --git a/src/gpio/gpio.c b/src/gpio/gpio.c index f13081f51..b54339b7a 100644 --- a/src/gpio/gpio.c +++ b/src/gpio/gpio.c @@ -1110,6 +1110,15 @@ mraa_gpio_mode(mraa_gpio_context dev, mraa_gpio_mode_t mode) case MRAA_GPIOD_OPEN_SOURCE: flags |= GPIOHANDLE_REQUEST_OPEN_SOURCE; break; + case MRAA_GPIO_PULLUP: + flags |= GPIOHANDLE_REQUEST_BIAS_PULL_UP; + break; + case MRAA_GPIO_PULLDOWN: + flags |= GPIOHANDLE_REQUEST_BIAS_PULL_DOWN; + break; + case MRAA_GPIOD_BIAS_DISABLE: + flags |= GPIOHANDLE_REQUEST_BIAS_DISABLE; + break; default: return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED; } diff --git a/src/gpio/gpio_chardev.c b/src/gpio/gpio_chardev.c index 9f727de71..0d12b8abb 100644 --- a/src/gpio/gpio_chardev.c +++ b/src/gpio/gpio_chardev.c @@ -429,6 +429,24 @@ mraa_is_gpio_line_open_source(mraa_gpiod_line_info* linfo) return (linfo->flags & GPIOLINE_FLAG_OPEN_SOURCE); } +mraa_boolean_t +mraa_is_gpio_line_bias_pull_up(mraa_gpiod_line_info* linfo) +{ + return (linfo->flags & GPIOLINE_FLAG_BIAS_PULL_UP); +} + +mraa_boolean_t +mraa_is_gpio_line_bias_pull_down(mraa_gpiod_line_info* linfo) +{ + return (linfo->flags & GPIOLINE_FLAG_BIAS_PULL_DOWN); +} + +mraa_boolean_t +mraa_is_gpio_line_bias_disable(mraa_gpiod_line_info* linfo) +{ + return (linfo->flags & GPIOLINE_FLAG_BIAS_DISABLE); +} + static int dir_filter(const struct dirent* dir) {