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Added more test cases.
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4 files changed

+136
-5
lines changed

4 files changed

+136
-5
lines changed

tests/unit/Design.py

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@
3535
from pySVModel import SystemVerilogVersion
3636
from pyVHDLModel import VHDLVersion
3737

38-
from pyEDAA.ProjectModel import Design, File, Project
38+
from pyEDAA.ProjectModel import Design, File, Project, Attribute
3939

4040

4141
if __name__ == "__main__": # pragma: no cover
@@ -145,3 +145,46 @@ def test_Design(self):
145145
design = Design("design", directory=Path("designA"), project=project)
146146

147147
design.Validate()
148+
149+
150+
class Attr(Attribute):
151+
pass
152+
153+
154+
class Attributes(TestCase):
155+
def test_AddAttribute_WrongType(self):
156+
design = Design("design")
157+
158+
with self.assertRaises(TypeError):
159+
design["attr"] = 5
160+
161+
def test_AddAttribute_Normal(self):
162+
design = Design("design")
163+
164+
design[Attr] = 5
165+
166+
def test_GetAttribute_WrongType(self):
167+
design = Design("design")
168+
design[Attr] = 5
169+
170+
with self.assertRaises(TypeError):
171+
_ = design["attr"]
172+
173+
def test_GetAttribute_Normal(self):
174+
design = Design("design")
175+
design[Attr] = 5
176+
177+
_ = design[Attr]
178+
179+
def test_DelAttribute_WrongType(self):
180+
design = Design("design")
181+
design[Attr] = 5
182+
183+
with self.assertRaises(TypeError):
184+
del design["attr"]
185+
186+
def test_DelAttribute_Normal(self):
187+
design = Design("design")
188+
design[Attr] = 5
189+
190+
del design[Attr]

tests/unit/File.py

Lines changed: 45 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
from pathlib import Path
3333
from unittest import TestCase
3434

35-
from pyEDAA.ProjectModel import Design, FileSet, File, Project, FileTypes
35+
from pyEDAA.ProjectModel import Design, FileSet, File, Project, FileTypes, Attribute
3636
from pyEDAA.ProjectModel.Attributes import KeyValueAttribute
3737

3838

@@ -155,14 +155,57 @@ def test_File(self):
155155
file.Validate()
156156

157157

158+
class Attr(Attribute):
159+
pass
160+
161+
158162
class Attributes(TestCase):
163+
def test_AddAttribute_WrongType(self):
164+
file = File(Path("file.txt"))
165+
166+
with self.assertRaises(TypeError):
167+
file["attr"] = 5
168+
169+
def test_AddAttribute_Normal(self):
170+
file = File(Path("file.txt"))
171+
172+
file[Attr] = 5
173+
174+
def test_GetAttribute_WrongType(self):
175+
file = File(Path("file.txt"))
176+
file[Attr] = 5
177+
178+
with self.assertRaises(TypeError):
179+
_ = file["attr"]
180+
181+
def test_GetAttribute_Normal(self):
182+
file = File(Path("file.txt"))
183+
file[Attr] = 5
184+
185+
_ = file[Attr]
186+
187+
def test_DelAttribute_WrongType(self):
188+
file = File(Path("file.txt"))
189+
file[Attr] = 5
190+
191+
with self.assertRaises(TypeError):
192+
del file["attr"]
193+
194+
def test_DelAttribute_Normal(self):
195+
file = File(Path("file.txt"))
196+
file[Attr] = 5
197+
198+
del file[Attr]
199+
200+
201+
class AttributeResolution(TestCase):
159202
def test_AttachedToFile(self):
160203
project = Project("project", rootDirectory=Path("project"))
161204
design = Design("design", directory=Path("designA"), project=project)
162205
fileSet = FileSet("fileset", design=design)
163206
file = File(Path("file_A1.vhdl"), fileSet=fileSet)
164207

165-
file._attributes[KeyValueAttribute] = KeyValueAttribute()
208+
file[KeyValueAttribute] = KeyValueAttribute()
166209

167210
attribute = file[KeyValueAttribute]
168211
attribute["id1"] = "5"

tests/unit/FileSet.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,9 @@
3535
from pySVModel import SystemVerilogVersion
3636
from pyVHDLModel import VHDLVersion
3737

38-
from pyEDAA.ProjectModel import Design, FileSet, File, FileTypes, TextFile, Project, VHDLLibrary, Attribute
38+
from pyEDAA.ProjectModel import Design, FileSet, File, FileTypes, TextFile, Project, VHDLLibrary, Attribute
39+
from pyEDAA.ProjectModel.Attributes import KeyValueAttribute
40+
3941

4042
if __name__ == "__main__": # pragma: no cover
4143
print("ERROR: you called a testcase declaration file as an executable module.")

tests/unit/Project.py

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@
3535
from pySVModel import SystemVerilogVersion
3636
from pyVHDLModel import VHDLVersion
3737

38-
from pyEDAA.ProjectModel import Project
38+
from pyEDAA.ProjectModel import Project, Attribute
3939

4040

4141
if __name__ == "__main__": # pragma: no cover
@@ -113,3 +113,46 @@ def test_Project(self):
113113
project = Project("project", rootDirectory=Path("project"))
114114

115115
project.Validate()
116+
117+
118+
class Attr(Attribute):
119+
pass
120+
121+
122+
class Attributes(TestCase):
123+
def test_AddAttribute_WrongType(self):
124+
project = Project("project")
125+
126+
with self.assertRaises(TypeError):
127+
project["attr"] = 5
128+
129+
def test_AddAttribute_Normal(self):
130+
project = Project("project")
131+
132+
project[Attr] = 5
133+
134+
def test_GetAttribute_WrongType(self):
135+
project = Project("project")
136+
project[Attr] = 5
137+
138+
with self.assertRaises(TypeError):
139+
_ = project["attr"]
140+
141+
def test_GetAttribute_Normal(self):
142+
project = Project("project")
143+
project[Attr] = 5
144+
145+
_ = project[Attr]
146+
147+
def test_DelAttribute_WrongType(self):
148+
project = Project("project")
149+
project[Attr] = 5
150+
151+
with self.assertRaises(TypeError):
152+
del project["attr"]
153+
154+
def test_DelAttribute_Normal(self):
155+
project = Project("project")
156+
project[Attr] = 5
157+
158+
del project[Attr]

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