Updated package references after renaming pySystemVerilogModel to pySVModel.

Author: Paebbels

README.md

@@ -33,7 +33,17 @@
 
 
 ```python
-print(some.python.code.here())
+from pathlib import Path
+from pyEDAA.ProjectModel import Project, Design, FileSet, VHDLSourceFile
+
+projectPath = Path("temp/project")
+project = Project("project", rootDirectory=projectPath)
+design = Design("design", project=project)
+fileset = FileSet("uart", Path("src/uart"), design=design)
+
+for vhdlFilePath in fileset.ResolvedPath.glob("*.vhdl"):
+	vhdlFile = VHDLSourceFile(vhdlFilePath)
+	fileset.AddFile(vhdlFile)
 ```
 
 

doc/Dependency.rst

@@ -35,7 +35,7 @@ pyEDAA.ProjectModel Package
 |                                                       |             |                                                                                   |   * `dill <https://github.com/uqfoundation/dill>`__ (`BSD 3-clause <https://github.com/uqfoundation/dill/blob/master/LICENSE>`__) |
 |                                                       |             |                                                                                   |   * `six <https://github.com/benjaminp/six>`__ (`MIT <https://github.com/benjaminp/six/blob/master/LICENSE>`__)                   |
 +-------------------------------------------------------+-------------+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
-| `pySVModel <https://github.com/edaa-org/pySVModel>`__ | ≥0.2.2      | `Apache License, 2.0 <https://github.com/VHDL/pyVHDLModel/blob/master/LICENSE>`__ | * `pydecor <https://github.com/mplanchard/pydecor>`__ (`MIT <https://github.com/mplanchard/pydecor/blob/master/LICENSE>`__)       |
+| `pySVModel <https://github.com/edaa-org/pySVModel>`__ | ≥0.3.0      | `Apache License, 2.0 <https://github.com/VHDL/pyVHDLModel/blob/master/LICENSE>`__ | * `pydecor <https://github.com/mplanchard/pydecor>`__ (`MIT <https://github.com/mplanchard/pydecor/blob/master/LICENSE>`__)       |
 |                                                       |             |                                                                                   |                                                                                                                                   |
 |                                                       |             |                                                                                   |   * `dill <https://github.com/uqfoundation/dill>`__ (`BSD 3-clause <https://github.com/uqfoundation/dill/blob/master/LICENSE>`__) |
 |                                                       |             |                                                                                   |   * `six <https://github.com/benjaminp/six>`__ (`MIT <https://github.com/benjaminp/six/blob/master/LICENSE>`__)                   |

pyEDAA/ProjectModel/__init__.py

@@ -34,7 +34,7 @@
 from pathlib import Path
 from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any
 
-from pySystemVerilogModel import VerilogVersion, SystemVerilogVersion
+from pySVModel import VerilogVersion, SystemVerilogVersion
 from pyVHDLModel import VHDLVersion
 from pydecor import export
 

requirements.txt

@@ -1,4 +1,4 @@
 pydecor>=2.0.1
 
 pyVHDLModel>=0.13.2
-pySystemVerilogModel>=0.2.1
+pySVModel>=0.3.0

tests/unit/Design.py

@@ -32,7 +32,7 @@
 from pathlib import Path
 from unittest import TestCase
 
-from pySystemVerilogModel import VerilogVersion, SystemVerilogVersion
+from pySVModel import VerilogVersion, SystemVerilogVersion
 from pyVHDLModel import VHDLVersion
 
 from pyEDAA.ProjectModel import Design, File, Project

tests/unit/FileSet.py

@@ -32,7 +32,7 @@
 from pathlib import Path
 from unittest import TestCase
 
-from pySystemVerilogModel import VerilogVersion, SystemVerilogVersion
+from pySVModel import VerilogVersion, SystemVerilogVersion
 from pyVHDLModel import VHDLVersion
 
 from pyEDAA.ProjectModel import Design, FileSet, File, FileTypes, TextFile, Project, VHDLLibrary

tests/unit/Files.py

@@ -33,7 +33,7 @@
 from unittest import TestCase
 
 from pyVHDLModel import VHDLVersion
-from pySystemVerilogModel import VerilogVersion, SystemVerilogVersion
+from pySVModel import VerilogVersion, SystemVerilogVersion
 
 from pyEDAA.ProjectModel import FileSet, VHDLSourceFile, VHDLLibrary, VerilogSourceFile, SystemVerilogSourceFile, FileTypes
 

tests/unit/Project.py

@@ -32,7 +32,7 @@
 from pathlib import Path
 from unittest import TestCase
 
-from pySystemVerilogModel import VerilogVersion, SystemVerilogVersion
+from pySVModel import VerilogVersion, SystemVerilogVersion
 from pyVHDLModel import VHDLVersion
 
 from pyEDAA.ProjectModel import Project