@@ -34,7 +34,7 @@ such a model, while supporting multiple input sources.
34341 . The toplevel element is a ` Project ` , which contains one or multiple designs.
35352 . A ` Design ` is a variant of a project and contains filesets.
36363 . A ` FileSet ` contains files or further sub-filesets.
37- 4 . A ` File ` represents a single file. E.g. source files, configuration files, constraint files
37+ 4 . A ` File ` represents a single file. E.g. source files, configuration files, constraint files.
38385 . A ` VHDLLibrary ` represents a group of ` VHDLSourceFile ` s being compiled into the same VHDL library.
3939
4040![ img.png] ( doc/datamodel.png )
@@ -48,7 +48,7 @@ such a model, while supporting multiple input sources.
4848* Designs, filesets and files can use absolute or relative paths.
4949 * ` ResolvedPath ` returns the resolved absolute path to an object.
5050* Projects, designs, filesets and files can be validated (e.g. if the path exists).
51- * Projects, designs, filesets and files can hav user-defined attributes.
51+ * Projects, designs, filesets and files can have user-defined attributes.
5252 * User-defined attributes are resolved bottom-up.
5353
5454
@@ -111,6 +111,7 @@ for file in designA.Files(fileType=VHDLSourceFile):
111111## Contributors
112112* [ Patrick Lehmann] ( https://github.com/Paebbels ) (Maintainer)
113113* [ Unai Martinez-Corral] ( https://github.com/umarcor )
114+ * [ Stefan Unrein] ( https://github.com/stefanunrein )
114115* [ and more...] ( https://github.com/edaa-org/pyEDAA.ProjectModel/graphs/contributors )
115116
116117
0 commit comments