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PaebbelsPaebbels
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General code updates.
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+137
-82
lines changed

13 files changed

+137
-82
lines changed

‎.github/pull_request_template.md‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,30 @@
11
# New Features
2-
2+
3+
* tbd
34
* tbd
45

56
# Changes
67

8+
* tbd
79
* tbd
810

911
# Bug Fixes
1012

13+
* tbd
14+
* tbd
15+
16+
# Documentation
17+
18+
* tbd
19+
* tbd
20+
21+
# Unit Tests
22+
23+
* tbd
1124
* tbd
1225

1326
----------
14-
# Related PRs:
27+
# Related Issues and Pull-Requests
1528

1629
* tbd
30+
* tbd

‎.github/workflows/Pipeline.yml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ jobs:
4646
uses: pyTooling/Actions/.github/workflows/PublishTestResults.yml@dev
4747
needs:
4848
- UnitTesting
49+
with:
50+
additional_merge_args: '"--pytest=rewrite-dunder-init;reduce-depth:pytest.tests.unit"'
4951

5052
Package:
5153
uses: pyTooling/Actions/.github/workflows/Package.yml@dev

‎dist/requirements.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
wheel ~= 0.43
2-
twine ~= 5.0
1+
wheel ~= 0.44
2+
twine ~= 5.1

‎doc/Dependency.rst‎

Lines changed: 13 additions & 13 deletions
Large diffs are not rendered by default.

‎doc/conf.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
# ==============================================================================
6262
prologPath = Path("prolog.inc")
6363
try:
64-
with prologPath.open("r") as fileHandle:
64+
with prologPath.open("r", encoding="utf-8") as fileHandle:
6565
rst_prolog = fileHandle.read()
6666
except Exception as ex:
6767
print(f"[ERROR:] While reading '{prologPath}'.")

‎doc/index.rst‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ News
9898
* ProjectModel became first citizen of `EDA² <https://GitHub.com/edaa-org>`__ and got integrated into the `pyEDAA` namespace at PyPI.
9999

100100

101-
.. _contributors:
101+
.. _CONTRIBUTORS:
102102

103103
Contributors
104104
************
@@ -108,6 +108,8 @@ Contributors
108108
* `and more... <https://GitHub.com/VHDL/pyVHDLModel/graphs/contributors>`__
109109

110110

111+
.. _LICENSE:
112+
111113
License
112114
*******
113115

‎doc/requirements.txt‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
11
-r ../requirements.txt
22

3-
pyTooling ~= 6.1
3+
pyTooling ~= 7.0
44

55
# Enforce latest version on ReadTheDocs
6-
sphinx ~= 7.3
6+
sphinx ~= 8.1
7+
docutils ~= 0.21
78

89
# Sphinx Extenstions
9-
sphinxcontrib-mermaid>=0.7.1
10+
sphinxcontrib-mermaid ~= 1.0
1011
autoapi>=2.0.1
1112
sphinx_fontawesome>=0.0.6
12-
sphinx_autodoc_typehints ~= 2.1
13+
sphinx_autodoc_typehints ~= 2.5

‎pyEDAA/ProjectModel/OSVVM.py‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,9 @@ class OSVVMProjectFile(ProjectFile, TCLContent):
4646
def __init__(
4747
self,
4848
path: Path,
49-
project: Project = None,
50-
design: Design = None,
51-
fileSet: FileSet = None
49+
project: Nullable[Project] = None,
50+
design: Nullable[Design] = None,
51+
fileSet: Nullable[FileSet] = None
5252
):
5353
super().__init__(path, project, design, fileSet)
5454

@@ -154,7 +154,7 @@ def _Parse(self) -> List:
154154

155155
instructions: List = []
156156
print()
157-
with path.open("r") as file:
157+
with path.open("r", encoding="utf-8") as file:
158158
i = 1
159159
for line in file:
160160
line = line.lstrip()

‎pyEDAA/ProjectModel/Xilinx/Vivado.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -90,9 +90,9 @@ class VivadoProjectFile(ProjectFile, XMLContent):
9090
def __init__(
9191
self,
9292
path: Path,
93-
project: Project = None,
94-
design: Design = None,
95-
fileSet: FileSet = None
93+
project: Nullable[Project] = None,
94+
design: Nullable[Design] = None,
95+
fileSet: Nullable[FileSet] = None
9696
) -> None:
9797
super().__init__(path, project, design, fileSet)
9898

‎pyEDAA/ProjectModel/__init__.py‎

Lines changed: 50 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,10 @@
3939

4040
from os.path import relpath as path_relpath
4141
from pathlib import Path as pathlib_Path
42+
from sys import version_info
4243
from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any
4344

45+
from pyTooling.Common import getFullyQualifiedName
4446
from pyTooling.Decorators import export
4547
from pyTooling.MetaClasses import ExtendedType
4648
from pyTooling.Graph import Graph, Vertex
@@ -123,9 +125,9 @@ class File(metaclass=FileType, slots=True):
123125
def __init__(
124126
self,
125127
path: pathlib_Path,
126-
project: 'Project' = None,
127-
design: 'Design' = None,
128-
fileSet: 'FileSet' = None
128+
project: Nullable["Project"] = None,
129+
design: Nullable["Design"] = None,
130+
fileSet: Nullable["FileSet"] = None
129131
):
130132
self._fileType = getattr(FileTypes, self.__class__.__name__)
131133
self._path = path
@@ -266,7 +268,12 @@ def __getitem__(self, key: Type[Attribute]) -> Any:
266268
try:
267269
return self._attributes[key]
268270
except KeyError:
269-
return key.resolve(self, key)
271+
try:
272+
return key.resolve(self, key)
273+
except KeyError:
274+
attribute = key()
275+
self._attributes[key] = attribute
276+
return attribute
270277

271278
def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
272279
"""
@@ -405,7 +412,7 @@ class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
405412
_vhdlLibrary: Nullable['VHDLLibrary']
406413
_vhdlVersion: VHDLVersion
407414

408-
def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: VHDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
415+
def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: Nullable[VHDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
409416
super().__init__(path, project, design, fileSet)
410417

411418
if isinstance(vhdlLibrary, str):
@@ -427,7 +434,10 @@ def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] =
427434
elif vhdlLibrary is None:
428435
self._vhdlLibrary = None
429436
else:
430-
raise TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
437+
ex = TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
438+
if version_info >= (3, 11): # pragma: no cover
439+
ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.")
440+
raise ex
431441

432442
self._vhdlVersion = vhdlVersion
433443

@@ -513,7 +523,7 @@ def SVVersion(self, value: SystemVerilogVersion) -> None:
513523
class VerilogBaseFile(HDLSourceFile, HumanReadableContent):
514524
_version: SystemVerilogVersion
515525

516-
def __init__(self, path: pathlib_Path, version: SystemVerilogVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
526+
def __init__(self, path: pathlib_Path, version: Nullable[SystemVerilogVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
517527
super().__init__(path, project, design, fileSet)
518528

519529
self._version = version
@@ -550,7 +560,7 @@ class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent):
550560

551561
_srdlVersion: SystemRDLVersion
552562

553-
def __init__(self, path: pathlib_Path, srdlVersion: SystemRDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
563+
def __init__(self, path: pathlib_Path, srdlVersion: Nullable[SystemRDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
554564
super().__init__(path, project, design, fileSet)
555565

556566
self._srdlVersion = srdlVersion
@@ -684,16 +694,16 @@ class FileSet(metaclass=ExtendedType, slots=True):
684694
def __init__(
685695
self,
686696
name: str,
687-
topLevel: str = None,
688-
directory: pathlib_Path = pathlib_Path("."),
689-
project: 'Project' = None,
690-
design: 'Design' = None,
691-
parent: Nullable['FileSet'] = None,
692-
vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
693-
vhdlVersion: VHDLVersion = None,
694-
verilogVersion: SystemVerilogVersion = None,
695-
svVersion: SystemVerilogVersion = None,
696-
srdlVersion: SystemRDLVersion = None
697+
topLevel: Nullable[str] = None,
698+
directory: pathlib_Path = pathlib_Path("."),
699+
project: Nullable["Project"] = None,
700+
design: Nullable["Design"] = None,
701+
parent: Nullable['FileSet'] = None,
702+
vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
703+
vhdlVersion: Nullable[VHDLVersion] = None,
704+
verilogVersion: Nullable[SystemVerilogVersion] = None,
705+
svVersion: Nullable[SystemVerilogVersion] = None,
706+
srdlVersion: Nullable[SystemRDLVersion] = None
697707
):
698708
self._name = name
699709
self._topLevel = topLevel
@@ -902,11 +912,13 @@ def AddFile(self, file: File) -> None:
902912
raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
903913
elif file._fileSet is not None:
904914
ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
905-
ex.add_note(f"A file can't be assigned to another fileset.")
915+
if version_info >= (3, 11): # pragma: no cover
916+
ex.add_note(f"A file can't be assigned to another fileset.")
906917
raise ex
907918
elif file in self._set:
908919
ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
909-
ex.add_note(f"A file can't be added twice to a fileset.")
920+
if version_info >= (3, 11): # pragma: no cover
921+
ex.add_note(f"A file can't be added twice to a fileset.")
910922
raise ex
911923

912924
self._files.append(file)
@@ -1127,9 +1139,9 @@ class VHDLLibrary(metaclass=ExtendedType, slots=True):
11271139
def __init__(
11281140
self,
11291141
name: str,
1130-
project: 'Project' = None,
1131-
design: 'Design' = None,
1132-
vhdlVersion: VHDLVersion = None
1142+
project: Nullable["Project"] = None,
1143+
design: Nullable["Design"] = None,
1144+
vhdlVersion: Nullable[VHDLVersion] = None
11331145
):
11341146
self._name = name
11351147
if project is not None:
@@ -1236,7 +1248,10 @@ def AddDependency(self, library: 'VHDLLibrary') -> None:
12361248

12371249
def AddFile(self, vhdlFile: VHDLSourceFile) -> None:
12381250
if not isinstance(vhdlFile, VHDLSourceFile):
1239-
raise TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
1251+
ex = TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
1252+
if version_info >= (3, 11): # pragma: no cover
1253+
ex.add_note(f"Got type '{getFullyQualifiedName(vhdlFile)}'.")
1254+
raise ex
12401255

12411256
self._files.append(vhdlFile)
12421257

@@ -1344,13 +1359,13 @@ class Design(metaclass=ExtendedType, slots=True):
13441359
def __init__(
13451360
self,
13461361
name: str,
1347-
topLevel: str = None,
1348-
directory: pathlib_Path = pathlib_Path("."),
1349-
project: 'Project' = None,
1350-
vhdlVersion: VHDLVersion = None,
1351-
verilogVersion: SystemVerilogVersion = None,
1352-
svVersion: SystemVerilogVersion = None,
1353-
srdlVersion: SystemRDLVersion = None
1362+
topLevel: Nullable[str] = None,
1363+
directory: pathlib_Path = pathlib_Path("."),
1364+
project: Nullable["Project"] = None,
1365+
vhdlVersion: Nullable[VHDLVersion] = None,
1366+
verilogVersion: Nullable[SystemVerilogVersion] = None,
1367+
svVersion: Nullable[SystemVerilogVersion] = None,
1368+
srdlVersion: Nullable[SystemRDLVersion] = None
13541369
):
13551370
self._name = name
13561371
self._topLevel = topLevel
@@ -1687,10 +1702,10 @@ class Project(metaclass=ExtendedType, slots=True):
16871702
def __init__(
16881703
self,
16891704
name: str,
1690-
rootDirectory: pathlib_Path = pathlib_Path("."),
1691-
vhdlVersion: VHDLVersion = None,
1692-
verilogVersion: SystemVerilogVersion = None,
1693-
svVersion: SystemVerilogVersion = None
1705+
rootDirectory: pathlib_Path = pathlib_Path("."),
1706+
vhdlVersion: Nullable[VHDLVersion] = None,
1707+
verilogVersion: Nullable[SystemVerilogVersion] = None,
1708+
svVersion: Nullable[SystemVerilogVersion] = None
16941709
):
16951710
self._name = name
16961711
self._rootDirectory = rootDirectory

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