Skip to content

Commit 9e2c78b

Browse files
authored
Additions needed by Xilinx Vivado project files
2 parents cd2edd1 + e839cec commit 9e2c78b

File tree

5 files changed

+32
-14
lines changed

5 files changed

+32
-14
lines changed

doc/conf.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@ def _LatestTagName():
3636
return check_output(["git", "describe", "--abbrev=0", "--tags"], universal_newlines=True).strip()
3737

3838
# The full version, including alpha/beta/rc tags
39-
version = "0.1" # The short X.Y version.
40-
release = "0.1.1" # The full version, including alpha/beta/rc tags.
39+
version = "0.2" # The short X.Y version.
40+
release = "0.2.0" # The full version, including alpha/beta/rc tags.
4141
try:
4242
if _IsUnderGitControl:
4343
latestTagName = _LatestTagName()[1:] # remove prefix "v"

pyEDAA/ProjectModel/Xilinx/Vivado.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@
3636
from pyVHDLModel import VHDLVersion
3737
from pydecor import export
3838

39-
from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, File, Attribute
39+
from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute
4040
from pyEDAA.ProjectModel import File as Model_File
4141
from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
4242
from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile

pyEDAA/ProjectModel/__init__.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@
3939
from pydecor import export
4040

4141

42-
__version__ = "0.1.1"
42+
__version__ = "0.2.0"
4343

4444

4545
@export

setup.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@
4040
gitHubNamespace = "edaa-org"
4141
projectName = "ProjectModel"
4242
projectNameWithPrefix = "pyEDAA." + projectName
43-
version = "0.1.1"
43+
version = "0.2.0"
4444

4545
# Read README for upload to PyPI
4646
readmeFile = Path("README.md")

tests/unit/VivadoProject.py

Lines changed: 27 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -43,16 +43,34 @@
4343
class FileSets(TestCase):
4444
def test_Parsing(self):
4545
xprPath = Path.cwd() / "tests/VivadoProject/StopWatch/project/StopWatch.xpr"
46-
print()
47-
print(f"{xprPath}")
46+
# print()
47+
# print(f"{xprPath}")
4848
xprFile = VivadoProjectFile(xprPath)
4949
xprFile.Parse()
5050

5151
project = xprFile.ProjectModel
52-
print(f"Project: {project.Name}")
53-
for designName, design in project.Designs.items():
54-
print(f" Design: {designName}")
55-
for fileSetName, fileSet in design.FileSets.items():
56-
print(f" FileSet: {fileSetName}")
57-
for file in fileSet.Files():
58-
print(f" {file.ResolvedPath}")
52+
53+
self.assertEqual("StopWatch", project.Name)
54+
55+
designs = [d for d in project.Designs.values()]
56+
self.assertEqual(1, len(designs))
57+
58+
design = designs[0]
59+
self.assertEqual("default", design.Name)
60+
self.assertIs(project.DefaultDesign, design)
61+
62+
expectedFilsesetNames = (
63+
"default", "src_Encoder", "src_Display", "src_StopWatch", "const_Encoder", "const_Display", "const_StopWatch",
64+
"sim_StopWatch", "utils_1"
65+
)
66+
filesets = [fs for fs in design.FileSets.keys()]
67+
self.assertEqual(len(expectedFilsesetNames), len(filesets))
68+
self.assertSequenceEqual(expectedFilsesetNames, filesets)
69+
70+
# print(f"Project: {project.Name}")
71+
# for designName, design in project.Designs.items():
72+
# print(f" Design: {designName}")
73+
# for fileSetName, fileSet in design.FileSets.items():
74+
# print(f" FileSet: {fileSetName}")
75+
# for file in fileSet.Files():
76+
# print(f" {file.ResolvedPath}")

0 commit comments

Comments
 (0)