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The VerilogSourceFile and SystemVerilogSourceFile need a library attribute, the same as in the VHDLSourceFile. Could you add this to the HDLSourceFile class and remove it from the VHDLSourceFile class? This way, the VerilogSourceFile and SystemVerilogSourceFile will also inherit the library attribute. When you have the Verilog version it is also not necessary to have both a VerilogSourceFile and SystemVerilogSourceFile class. There needs to be either a Verilog include attribute or a VerilogIncludeFile class to handle Verilog include files.
class HDLIncludeFile(SourceFile):
pass
class VerilogIncludeFile(HDLIncludeFile, HumanReadableContent):
pass
class HDLSourceFile(SourceFile):
_library: HDLLibrary
class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
_version: VHDLVersion
class VerilogSourceFile(HDLSourceFile, HumanReadableContent):
_version: VerilogVersionMetadata
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