1- From 3b6052e852abc1384020eff979d4ee886defee91 Mon Sep 17 00:00:00 2001
1+ From 55d0e1e5a1e647321c13b3d346efbc7556def75c Mon Sep 17 00:00:00 2001
22From: Benjamin Leggett <
[email protected] >
3- Date: Thu, 31 Jul 2025 19:36:18 -0400
4- Subject: [PATCH] PAT detection workaround
3+ Date: Fri, 3 Oct 2025 23:06:24 -0400
4+ Subject: [PATCH] Use built-in PAT even on x86
55
66---
77 kernel-open/nvidia/nv-pat.c | 19 ++++++++++---------
88 1 file changed, 10 insertions(+), 9 deletions(-)
99
1010diff --git a/kernel-open/nvidia/nv-pat.c b/kernel-open/nvidia/nv-pat.c
11- index 1fa530d9..2dc5cee7 100644
11+ index 870dedbd..5a43bf21 100644
1212--- a/kernel-open/nvidia/nv-pat.c
1313+++ b/kernel-open/nvidia/nv-pat.c
1414@@ -40,12 +40,9 @@ int nv_pat_mode = NV_PAT_MODE_DISABLED;
@@ -28,8 +28,8 @@ index 1fa530d9..2dc5cee7 100644
2828 #define NV_WRITE_PAT_ENTRIES(pat1, pat2) wrmsr(0x277, (pat1), (pat2))
2929@@ -63,14 +60,14 @@ static inline void nv_disable_caches(unsigned long *cr4)
3030 wbinvd();
31- *cr4 = NV_READ_CR4 ();
32- if (*cr4 & 0x80) NV_WRITE_CR4 (*cr4 & ~0x80);
31+ *cr4 = __read_cr4 ();
32+ if (*cr4 & 0x80) __write_cr4 (*cr4 & ~0x80);
3333- __flush_tlb();
3434+ __flush_tlb_local();
3535 }
@@ -41,9 +41,9 @@ index 1fa530d9..2dc5cee7 100644
4141- __flush_tlb();
4242+ __flush_tlb_local();
4343 write_cr0((cr0 & 0x9fffffff));
44- if (cr4 & 0x80) NV_WRITE_CR4 (cr4);
44+ if (cr4 & 0x80) __write_cr4 (cr4);
4545 }
46- @@ -390 ,8 +387 ,12 @@ static int nv_determine_pat_mode(void)
46+ @@ -317 ,8 +314 ,12 @@ static int nv_determine_pat_mode(void)
4747 else if (PAT_WC_index != 0xf)
4848 {
4949 nv_printf(NV_DBG_ERRORS,
@@ -59,5 +59,5 @@ index 1fa530d9..2dc5cee7 100644
5959 else
6060 {
6161- -
62- 2.50.1
62+ 2.51.0
6363
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