diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 848d12a2c..ffa8ad996 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -46,6 +46,7 @@ jobs: - rock-5b - rock-5bplus - station-m3 + - vicharak-axon CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }} steps: - name: Checkout diff --git a/README.md b/README.md index 56da25577..d63f3dcd4 100644 --- a/README.md +++ b/README.md @@ -47,6 +47,7 @@ Note that this list is subject to change at any time as devices gain better supp - [Mixtile Blade 3](https://www.mixtile.com/blade-3) - [FriendlyELEC NanoPi M6](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_M6) - [Hinlink H88K](http://www.hinlink.com) +- [Vicharak Axon](https://vicharak.in/axon) # Supported OSes ## In ACPI mode @@ -222,6 +223,7 @@ In addition to the default paths above, it is possible to specify custom ones vi | `rk3588s-nanopi-r6s` | NanoPi R6S | | `rk3588s-nanopi-m6` | NanoPi M6 | | `rk3588-hinlink-h88k` | H88K | +| `rk3588-axon-linux` | Vicharak Axon | **Notes:** * The firmware applies some fix-ups to the DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied when providing overrides by other means, such as the Grub `devicetree` command. diff --git a/configs/vicharak-axon.conf b/configs/vicharak-axon.conf new file mode 100644 index 000000000..aea432d72 --- /dev/null +++ b/configs/vicharak-axon.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Vicharak/Axon/Axon.dsc +PLATFORM_NAME=Axon +SOC=RK3588 diff --git a/devicetree/vendor/README.md b/devicetree/vendor/README.md index c667cee20..315cf0c8b 100644 --- a/devicetree/vendor/README.md +++ b/devicetree/vendor/README.md @@ -16,5 +16,7 @@ * rk3588s-fydetab-duo: (note: dtb taken from the `noble` branch which is based on the rockchip 6.1 rkr3 bsp kernel) +* rk3588-axon: + ## License SPDX-License-Identifier: GPL-2.0-only diff --git a/devicetree/vendor/rk3588-axon-linux.dtb b/devicetree/vendor/rk3588-axon-linux.dtb new file mode 100644 index 000000000..2cb8154e0 Binary files /dev/null and b/devicetree/vendor/rk3588-axon-linux.dtb differ diff --git a/edk2-rockchip/Platform/Vicharak/Axon/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Vicharak/Axon/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000..35d333b08 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/edk2-rockchip/Platform/Vicharak/Axon/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Vicharak/Axon/AcpiTables/Dsdt.asl new file mode 100644 index 000000000..c93ce4d14 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/AcpiTables/Dsdt.asl @@ -0,0 +1,55 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C3" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C3) { + include ("Es8388.asl") + } + } +} + diff --git a/edk2-rockchip/Platform/Vicharak/Axon/Axon.Modules.fdf.inc b/edk2-rockchip/Platform/Vicharak/Axon/Axon.Modules.fdf.inc new file mode 100644 index 000000000..a07eacb5d --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/Axon.Modules.fdf.inc @@ -0,0 +1,17 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Utsav Balar +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + INF RuleOverride = DTB $(PLATFORM_DIRECTORY)/DeviceTree/Vendor.inf + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/edk2-rockchip/Platform/Vicharak/Axon/Axon.dsc b/edk2-rockchip/Platform/Vicharak/Axon/Axon.dsc new file mode 100644 index 000000000..c36c38900 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/Axon.dsc @@ -0,0 +1,148 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Utsav Balar +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Axon + PLATFORM_VENDOR = Vicharak + PLATFORM_GUID = 9c75d879-067d-4b8b-89f6-ea717829ea23 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # PCA95XX GPIO extender support + # I2C location configured by PCDs below. + # + DEFINE RK_PCA95XX_ENABLE = TRUE + + # + # RK3588-based platform + # + +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Axon" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Vicharak" + gRockchipTokenSpaceGuid.PcdFamilyName|"Axon" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://vicharak.in/" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-axon-linux.dtb" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x24, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x6, 0x3 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x0 + gRockchipTokenSpaceGuid.PcdPca95xxAddress|0x24 + gRockchipTokenSpaceGuid.PcdPca95xxBus|0x6 + gRockchipTokenSpaceGuid.PcdPca95xxType|"PCA9554" + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|FALSE + + # + # Display support flags and default values + # + gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({ + VOP_OUTPUT_IF_HDMI0, + VOP_OUTPUT_IF_HDMI1, + VOP_OUTPUT_IF_DP0 + })} + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43 + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + $(PLATFORM_DIRECTORY)/DeviceTree/Vendor.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/edk2-rockchip/Platform/Vicharak/Axon/DeviceTree/Vendor.inf b/edk2-rockchip/Platform/Vicharak/Axon/DeviceTree/Vendor.inf new file mode 100644 index 000000000..6954a35e1 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/DeviceTree/Vendor.inf @@ -0,0 +1,17 @@ +#/** @file +# +# Copyright (c) 2024, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = DeviceTree-Vendor + FILE_GUID = d58b4028-43d8-4e97-87d4-4e3716136580 + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Binaries] + BIN|devicetree/vendor/rk3588-axon-linux.dtb diff --git a/edk2-rockchip/Platform/Vicharak/Axon/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Vicharak/Axon/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 000000000..96ad58ad4 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,550 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + // vdd_gpu_s0 + RK8XX_VOLTAGE_INIT (MASTER_BUCK1, 950000), + // vdd_cpu_lit_s0 (Dynamically set from CpuPerformance) + // RK8XX_VOLTAGE_INIT(MASTER_BUCK2, 950000), + // vdd_log_s0 + RK8XX_VOLTAGE_INIT (MASTER_BUCK3, 750000), + // vdd_vdenc_s0 + RK8XX_VOLTAGE_INIT (MASTER_BUCK4, 750000), + // vdd_ddr_s0 + RK8XX_VOLTAGE_INIT (MASTER_BUCK5, 900000), + // vcc_2v0_pldo_s3 + RK8XX_VOLTAGE_INIT (MASTER_BUCK7, 2000000), + // vcc_3v3_s3 + RK8XX_VOLTAGE_INIT (MASTER_BUCK8, 3300000), + // vcc_1v8_s3 + RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000), + + // avcc_1v8_s0 + RK8XX_VOLTAGE_INIT (MASTER_PLDO1, 1800000), + // vcc_1v8_s0 + RK8XX_VOLTAGE_INIT (MASTER_PLDO2, 1800000), + // avdd_1v2_s0 + RK8XX_VOLTAGE_INIT (MASTER_PLDO3, 1200000), + // vcc_3v3_s0 + RK8XX_VOLTAGE_INIT (MASTER_PLDO4, 3300000), + // vccio_sd_s0 + RK8XX_VOLTAGE_INIT (MASTER_PLDO5, 3300000), + // pldo6_s3 + RK8XX_VOLTAGE_INIT (MASTER_PLDO6, 1800000), + + // vdd_0v75_s3 + RK8XX_VOLTAGE_INIT (MASTER_NLDO1, 750000), + // vdd_ddr_pll_s0 + RK8XX_VOLTAGE_INIT (MASTER_NLDO2, 850000), + // avdd_0v75_s0 + RK8XX_VOLTAGE_INIT (MASTER_NLDO3, 837500), + // vdd_0v85_s0 + RK8XX_VOLTAGE_INIT (MASTER_NLDO4, 850000), + // vdd_0v75_s0 + RK8XX_VOLTAGE_INIT (MASTER_NLDO5, 750000), + /* No dual PMICs on this platform */ +}; + +EFI_STATUS +EFIAPI +GetPca95xxProtocol ( + IN OUT PCA95XX_PROTOCOL **Pca95xxProtocl + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN HandleCount; + + /* Locate Handles of all PCA95XX_PROTOCOL producers */ + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gPca95xxProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__)); + return Status; + } + + DEBUG (( + DEBUG_INFO, + "%a: got %d PCA95XX_PROTOCOLs\n", + __FUNCTION__, + HandleCount + )); + + /* + * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute + * the consumer is not obliged to call CloseProtocol. + */ + Status = gBS->OpenProtocol ( + HandleBuffer[0], + &gPca95xxProtocolGuid, + (VOID **)Pca95xxProtocl, + HandleBuffer[0], + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + return Status; +} + +VOID EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = + // write_enable{0,1,2,3} + (0xFFFFUL << 16) | + // SDMMC_D0, SDMMC_D1, SDMMC_D2, SDMMC_D3 + (0x1111); + + BUS_IOC->GPIO4D_IOMUX_SEL_H = + // write_enable + (0x00FFUL << 16) | + // SDMMC_CLK, SDMMC_CMD + (0x0011); + + PMU1_IOC->GPIO0A_IOMUX_SEL_H = + // write_enable + (0x000FUL << 16) | + // SDMMC_DET + (0x0001); +} + +VOID EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = + // write_enable + (0xFFFFUL << 16) | + // EMMC_CMD, EMMC_CLKOUT, EMMC_DATASTROBE, EMMC_RSTN + (0x1111); + + BUS_IOC->GPIO2D_IOMUX_SEL_L = + // write_enable{0,1,2,3} + (0xFFFFUL << 16) | + // EMMC_D0, EMMC_D1, EMMC_D2, EMMC_D3 + (0x1111); + + BUS_IOC->GPIO2D_IOMUX_SEL_H = + // write_enable{4,5,6,7} + (0xFFFFUL << 16) | + // EMMC_D4, EMMC_D5, EMMC_D6, EMMC_D7 + (0x1111); +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + PMU1_IOC->GPIO0A_IOMUX_SEL_H = + // write_enable + (0x0FF0UL << 16) | + // SPI2_MOSI_M2, SPI2_CLK_M2 + (0x0110); + + PMU1_IOC->GPIO0B_IOMUX_SEL_L = + // write_enable + (0xF0FFUL << 16) | + // SPI2_MISO_M2, SPI2_CS0_M2, SPI2_CS1_M2 + (0x1011); + + MmioWrite32 ( + NS_CRU_BASE + CRU_CLKSEL_CON59, + (0x00C0UL << 16) | (0x0080) + ); +} + +VOID EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init (); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); + RegCfgIndex++) + { + RK806RegulatorInit (rk806_init_data[RegCfgIndex]); + } +} + +VOID EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts); + + RK806RegulatorInit (Rk806CpuLittleSupply); +} + +VOID EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* No NOR flash here */ +} + +VOID EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */ + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */ + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */ + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2 + GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2 + break; + case 1: + GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2 + GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2 + break; + case 3: + GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0 + GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0 + break; + case 6: + GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0 + GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + Status = GetPca95xxProtocol (&Pca95xxProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status)); + } else { + /* USB-C */ + Pca95xxProtocol->GpioProtocol.Set ( + &Pca95xxProtocol->GpioProtocol, + 6, /* vbus5v0_typec0_pwr_en */ + GPIO_MODE_OUTPUT_0 + ); + + gBS->Stall (1200000); + + Pca95xxProtocol->GpioProtocol.Set ( + &Pca95xxProtocol->GpioProtocol, + 6, /* vbus5v0_typec0_pwr_en */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set ( + &Pca95xxProtocol->GpioProtocol, + 4, /* vbus5v0_typec0_pwr_en */ + GPIO_MODE_OUTPUT_0 + ); + + gBS->Stall (1200000); + + Pca95xxProtocol->GpioProtocol.Set ( + &Pca95xxProtocol->GpioProtocol, + 4, /* vbus5v0_typec0_pwr_en */ + GPIO_MODE_OUTPUT_1 + ); + + } +} + +#define USB2PHY0_GRF_BASE 0xFD5D0000 +#define PMU0_GRF_SOC_CON2 0x00000008 +#define USB2PHY1_GRF_BASE 0xFD5D4000 +#define USB2PHY2_GRF_BASE 0xFD5D8000 +#define USB2PHY3_GRF_BASE 0xFD5DC000 +#define PMU1_CRU_BASE 0xFD7F0000 +#define PMU1CRU_SOFTRST_CON04 0x00000A10 + +VOID EFIAPI +Usb2PhyResume ( + VOID + ) +{ + // Set pmu0_mem_cfg_hdsprf to RA + MmioWrite32 ( + USB2PHY0_GRF_BASE + PMU0_GRF_SOC_CON2, + (0x2000UL << 16) | 0x0000 + ); + MmioWrite32 ( + USB2PHY1_GRF_BASE + PMU0_GRF_SOC_CON2, + (0x2000UL << 16) | 0x0000 + ); + MmioWrite32 ( + USB2PHY2_GRF_BASE + PMU0_GRF_SOC_CON2, + (0x2000UL << 16) | 0x0000 + ); + MmioWrite32 ( + USB2PHY3_GRF_BASE + PMU0_GRF_SOC_CON2, + (0x2000UL << 16) | 0x0000 + ); + + MmioWrite32 (PMU1_CRU_BASE + PMU1CRU_SOFTRST_CON04, 0x07000700); + MmioWrite32 (PMU1_CRU_BASE + PMU1CRU_SOFTRST_CON04, 0x07000000); +} + +VOID EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: // U.2 + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinSetDirection (0, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + } +} + +VOID EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (0, GPIO_PIN_PB2, Enable); + break; + } +} + +VOID EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (4, GPIO_PIN_PA5, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + } +} + +VOID +EFIAPI +HdmiTxIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec + GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE); + GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd + GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE); + GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl + GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE); + GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda + GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE); + break; + case 1: + GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec + GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE); + GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd + GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE); + GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl + GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE); + GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda + GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE); + break; + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + // TODO: +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + // TODO: +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + Status = GetPca95xxProtocol (&Pca95xxProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%s failed to get PCA9555! (%d)\n", __FUNCTION__, Status)); + } else { + Pca95xxProtocol->GpioProtocol.Set ( + &Pca95xxProtocol->GpioProtocol, + 1, /* Status Led */ + GPIO_MODE_OUTPUT_0 + ); + } +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + Status = GetPca95xxProtocol (&Pca95xxProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%s failed to get PCA9555! (%d)\n", __FUNCTION__, Status)); + } else { + Pca95xxProtocol->GpioProtocol.Set ( + &Pca95xxProtocol->GpioProtocol, + 1, /* Status Led */ + Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0 + ); + } +} + +CONST EFI_GUID * +EFIAPI +PlatformGetDtbFileGuid ( + IN UINT32 CompatMode + ) +{ + STATIC CONST EFI_GUID VendorDtbFileGuid = { + // DeviceTree/Vendor.inf + 0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 } + }; + + switch (CompatMode) { + case FDT_COMPAT_MODE_VENDOR: + return &VendorDtbFileGuid; + case FDT_COMPAT_MODE_MAINLINE: + return NULL; + } + + return NULL; +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // Jack detect +} diff --git a/edk2-rockchip/Platform/Vicharak/Axon/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/edk2-rockchip/Platform/Vicharak/Axon/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 000000000..b52c591f2 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Axon/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,38 @@ +#/** @file +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Protocols] + gPca95xxProtocolGuid + +[Sources.common] + RockchipPlatformLib.c diff --git a/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.bmp b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 000000000..ba5118b8e Binary files /dev/null and b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.bmp differ diff --git a/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.c b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.c new file mode 100644 index 000000000..c2e65dd2d --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.c @@ -0,0 +1,171 @@ +/** @file + Logo DXE Driver, install Edkii Platform Logo protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if ((Instance == NULL) || (Image == NULL) || + (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx ( + mHiiImageEx, + mHiiHandle, + mLogos[Current].ImageId, + Image + ); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol ( + &gEfiHiiDatabaseProtocolGuid, + NULL, + (VOID **)&HiiDatabase + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol ( + &gEfiHiiImageExProtocolGuid, + NULL, + (VOID **)&mHiiImageEx + ); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol ( + ImageHandle, + &gEfiHiiPackageListProtocolGuid, + (VOID **)&PackageList, + ImageHandle, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n" + )); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList ( + HiiDatabase, + PackageList, + NULL, + &mHiiHandle + ); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEdkiiPlatformLogoProtocolGuid, + &mPlatformLogo, + NULL + ); + } + + return Status; +} diff --git a/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.idf b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.idf new file mode 100644 index 000000000..c2d909624 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/LogoDxe.inf b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 000000000..e7a35de10 --- /dev/null +++ b/edk2-rockchip/Platform/Vicharak/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid