@@ -53,25 +53,31 @@ endmodule
5353module OUTREG #(parameter WIDTH= 32 )
5454(
5555 input wire CLK, // FO: 8
56+ input wire EN,
5657 input wire [WIDTH- 1 :0 ] Di,
57- output wire [WIDTH- 1 :0 ] Do
58+ output wire [WIDTH- 1 :0 ] Do
59+
5860);
5961 localparam BYTE_CNT = WIDTH / 8 ;
6062
6163 wire [BYTE_CNT- 1 :0 ] CLKBUF;
64+ wire [BYTE_CNT- 1 :0 ] GCLK;
65+
6266 wire CLK_buf;
6367
6468 sky130_fd_sc_hd__clkbuf_4 Root_CLKBUF (.X (CLK_buf), .A(CLK));
6569 sky130_fd_sc_hd__clkbuf_4 Do_CLKBUF [BYTE_CNT- 1 :0 ] (.X (CLKBUF), .A(CLK_buf) );
6670
71+ sky130_fd_sc_hd__dlclkp_4 CG [BYTE_CNT- 1 :0 ] ( .CLK(CLKBUF), .GCLK(GCLK), .GATE(EN) );
72+
6773 generate
6874 genvar i;
6975 for (i= 0 ; i< BYTE_CNT; i= i+ 1 ) begin : OUTREG_BYTE
7076 `ifndef NO_DIODES
7177 (* keep = "true" * )
7278 sky130_fd_sc_hd__diode_2 DIODE [7 :0 ] (.DIODE(Di[(i+ 1 )* 8 - 1 :i* 8 ]));
7379 `endif
74- sky130_fd_sc_hd__dfxtp_1 Do_FF [7 :0 ] ( .D(Di[(i+ 1 )* 8 - 1 :i* 8 ]), .Q(Do[(i+ 1 )* 8 - 1 :i* 8 ]), .CLK(CLKBUF [i]) );
80+ sky130_fd_sc_hd__dfxtp_1 Do_FF [7 :0 ] ( .D(Di[(i+ 1 )* 8 - 1 :i* 8 ]), .Q(Do[(i+ 1 )* 8 - 1 :i* 8 ]), .CLK(GCLK [i]) );
7581 end
7682 endgenerate
7783endmodule
@@ -273,7 +279,7 @@ module RAM16 #( parameter USE_LATCH=1,
273279 end
274280 endgenerate
275281
276- OUTREG #(.WIDTH(WSIZE*8 )) Do0_REG ( .CLK(CLK_buf), .Di(Do0_pre), .Do(Do0) );
282+ OUTREG #(.WIDTH(WSIZE*8 )) Do0_REG ( .CLK(CLK_buf), .EN(EN0_buf), . Di(Do0_pre), .Do(Do0) );
277283
278284endmodule
279285
@@ -310,7 +316,8 @@ module DFFRAM #( parameter USE_LATCH = 1,
310316 (* keep * ) CLKBUF_16 long_wire_repair (.X (CLK_buf), .A(CLK));
311317
312318 always @(posedge CLK_buf)
313- last_SEL0 <= SEL0;
319+ if (EN0)
320+ last_SEL0 <= SEL0;
314321
315322 generate
316323 genvar i;
0 commit comments