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Merge pull request #28 from Manarabdelaty/incr_user_ram_blocks
Updated default number of sram blocks for the user area
2 parents 7e1c2ca + 75208d5 commit 41877c9

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4 files changed

+7
-3
lines changed

4 files changed

+7
-3
lines changed

verilog/rtl/defines.v

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@@ -11,4 +11,4 @@
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// Number of RAM blocks for the mgmt_core
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`define MGMT_BLOCKS 2
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`define USER_BLOCKS 4
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`define USER_BLOCKS 6

verilog/rtl/mgmt_soc.v

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@@ -220,6 +220,8 @@ module mgmt_soc (
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};
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parameter [(`USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
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{24'h 50_0000},
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{24'h 40_0000},
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{24'h 30_0000},
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{24'h 20_0000},
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{24'h 10_0000},

verilog/rtl/storage.v

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@@ -3,7 +3,7 @@
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Management area has R/W access for MGMT_BLOCKS and RO access for USER_BLOCKS */
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module storage #(
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parameter USER_BLOCKS = 4, // R/W access
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parameter USER_BLOCKS = 6, // R/W access
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parameter MGMT_BLOCKS = 2 // R/W access
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) (
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// MGMT_AREA R/W Interface (MGMT_BLOCKS)

verilog/rtl/storage_bridge_wb.v

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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module storage_bridge_wb #(
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parameter USER_BLOCKS = 4,
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parameter USER_BLOCKS = 6,
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parameter MGMT_BLOCKS = 2,
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parameter MGMT_BASE_ADR = 32'h 0100_0000,
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parameter USER_BASE_ADR = 32'h 0200_0000
@@ -40,6 +40,8 @@ module storage_bridge_wb #(
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};
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parameter [(USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
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{24'h 50_0000},
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{24'h 40_0000},
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{24'h 30_0000},
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{24'h 20_0000},
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{24'h 10_0000},

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