diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index c9c6996d5..fce2ec20b 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -19,7 +19,7 @@
 #include <defs.h>
 #include <stub.c>
 
-#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_secondary (*(volatile uint32_t*)0x30000000)
 
 /*
 	Wishbone Test:
@@ -82,9 +82,9 @@ void main()
     // Flag start of the test
 	reg_mprj_datal = 0xAB600000;
 
-    reg_mprj_slave = 0x00002710;
+    reg_mprj_secondary = 0x00002710;
     reg_mprj_datal = 0xAB610000;
-    if (reg_mprj_slave == 0x2B3D) {
+    if (reg_mprj_secondary == 0x2B3D) {
         reg_mprj_datal = 0xAB610000;
     }
 }
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 7704be8d5..61f4f7968 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -43,7 +43,7 @@ module user_proj_example #(
     inout vssd1,	// User area 1 digital ground
 `endif
 
-    // Wishbone Slave ports (WB MI A)
+    // Wishbone Secondary ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,
     input wbs_stb_i,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 14e4dee2a..dca68a5ee 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -43,7 +43,7 @@ module user_project_wrapper #(
     inout vssd2,	// User area 2 digital ground
 `endif
 
-    // Wishbone Slave ports (WB MI A)
+    // Wishbone Secondary ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,
     input wbs_stb_i,
@@ -91,7 +91,7 @@ user_proj_example mprj (
     .wb_clk_i(wb_clk_i),
     .wb_rst_i(wb_rst_i),
 
-    // MGMT SoC Wishbone Slave
+    // MGMT SoC Wishbone Secondary
 
     .wbs_cyc_i(wbs_cyc_i),
     .wbs_stb_i(wbs_stb_i),