diff --git a/.gitignore b/.gitignore
index 9ccca4b3e..47d68ba7a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,3 +3,6 @@ precheck_results
 *.lst
 *.vcd
 *.gtkw
+*.vvp
+*.log
+build
diff --git a/Makefile b/Makefile
index c7e95e587..f5226d195 100644
--- a/Makefile
+++ b/Makefile
@@ -15,9 +15,10 @@
 # SPDX-License-Identifier: Apache-2.0
 MAKEFLAGS+=--warn-undefined-variables
 
-CARAVEL_ROOT?=$(PWD)/caravel
+CARAVEL_USER_PROJECT_ROOT:=$(shell readlink -f .)
+CARAVEL_ROOT?=${CARAVEL_USER_PROJECT_ROOT}/caravel
 PRECHECK_ROOT?=${HOME}/mpw_precheck
-MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+MCW_ROOT?=${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper
 SIM?=RTL
 
 export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
@@ -59,6 +60,27 @@ install:
 simenv:
 	docker pull efabless/dv_setup:latest
 
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && \
+	export SIM=${SIM} && ${MAKE} sim"
+
+FIRMWARE_SOURCE_DIR := ${CARAVEL_USER_PROJECT_ROOT}/caravel_firmware
+FIRMWARE_BUILD_DIR := ${CARAVEL_USER_PROJECT_ROOT}/build
+FIRMWARE_GENERATOR ?= 'Unix Makefiles'
+
+.PHONY: configure-firmware
+configure_firmware:
+	cmake -DCMAKE_TOOLCHAIN_FILE=${FIRMWARE_SOURCE_DIR}/cmake/vexriscv_toolchain.cmake \
+	-B${FIRMWARE_BUILD_DIR} \
+	-G${FIRMWARE_GENERATOR} \
+	${FIRMWARE_SOURCE_DIR}
+
+.PHONY: firmware
+firmware: configure_firmware
+	cmake --build ${FIRMWARE_BUILD_DIR}
+
 .PHONY: setup
 setup: install check-env install_mcw pdk openlane
 
@@ -82,12 +104,12 @@ docker_run_verify=\
 		-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
 		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
 		-e TOOLS=/opt/riscv32i \
-		-e DESIGNS=$(TARGET_PATH) \
-		-e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
+		-e DESIGNS=${TARGET_PATH} \
+		-e CORE_VERILOG_PATH=${TARGET_PATH}/mgmt_core_wrapper/verilog \
 		-e GCC_PREFIX=riscv32-unknown-elf \
-		-e MCW_ROOT=$(MCW_ROOT) \
-		-u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \
-		sh -c $(verify_command)
+		-e MCW_ROOT=${MCW_ROOT} \
+		efabless/dv_setup:latest \
+		sh -c ${VERIFY_COMMAND}
 
 .PHONY: harden
 harden: $(blocks)
@@ -204,6 +226,3 @@ check-pdk:
 help:
 	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
-
-
-
diff --git a/caravel_firmware/CMakeLists.txt b/caravel_firmware/CMakeLists.txt
new file mode 100644
index 000000000..510862d5a
--- /dev/null
+++ b/caravel_firmware/CMakeLists.txt
@@ -0,0 +1,7 @@
+cmake_minimum_required(VERSION 3.16)
+project(CaravelFirmware VERSION 0.1.0 LANGUAGES C CXX ASM)
+
+set(CMAKE_C_STANDARD 11)
+set(CMAKE_CXX_STANDARD 11)
+
+add_subdirectory(src)
diff --git a/caravel_firmware/README.md b/caravel_firmware/README.md
new file mode 100644
index 000000000..e87183e63
--- /dev/null
+++ b/caravel_firmware/README.md
@@ -0,0 +1,27 @@
+# Caravel firmware
+The files in this directory are a common place for firmware code to be written. Whilst a subdirectory now this directory should be made a separate repo and then "submoduled" in any caravel repo that requires it. This allows common aspects of the firmware to be developed independently of the design, but the design specifies exactly which version of firmware is relevant to the current state of the design.
+
+## Motivation
+The reason to move firmware builds into a single place is twofold:
+* All configuration necessary to compile the firmware is in one place. For users developing firmware it then becomes transparent what compiler flags, linker scripts etc... are required to compile their own firmware.
+* Firmware development continues independently of the design. Abstract classes and structs that are independent of the design can be developed separately to the design and the design specifies when it's ready to take those updates.
+
+## Building
+To build the firmware you need to install cmake (and optionally Ninja) and ensure that the GCC toolchain executables are added to the PATH. Cmake is a fantastic tool which is able to generate build scripts for multiple toolchains (GNU Make, Ninja, MSVC, Xcode) so that firmware can be built on any platform. For more information please consult [the cmake documentation](https://cmake.org/).
+
+### Configuration
+The build with cmake takes place in two parts; configuration, which generates the build files and building which does the compilation. To configure the cmake build run
+```bash
+cmake -DCMAKE_TOOLCHAIN_FILE=cmake/vexriscv_toolchain.cmake -Bbuild -GNinja
+```
+from this directory. This can be explained as:
+* `-DCMAKE_TOOLCHAIN_FILE=cmake/vexriscv_toolchain.cmake` tells cmake to load the toochain as specified by `vexriscv_toolchain.cmake`. This file just tells cmake where to find the compiler and some global additional compiler flags.
+* `-Bbuild` tells cmake to put the build files in a directory called `build`
+* `-GNinja` tells cmake which generator to use. This is optional and defaults to  whatever host you are building on, for Linux systems this is GNU Make. Ninja is a  fast and efficient alternative and I suggest using it.
+
+### Building
+Now that cmake has configured the build, the source code can be compiled. To do this simply run
+```bash
+cmake --build build/
+```
+which tells cmake to build all things in the `build/` directory. All the build artifacts are placed in the `build/` directory with the same layout as this directory.
diff --git a/caravel_firmware/cmake/vexriscv_toolchain.cmake b/caravel_firmware/cmake/vexriscv_toolchain.cmake
new file mode 100644
index 000000000..65ef0fac4
--- /dev/null
+++ b/caravel_firmware/cmake/vexriscv_toolchain.cmake
@@ -0,0 +1,18 @@
+# To use this file you must invoke cmake with -DCMAKE_TOOLCHAIN_FILE like so:
+# (From build directory)
+# `cmake -DCMAKE_TOOLCHAIN_FILE=cmake/riscv_toolchain.cmake .`
+
+find_path(RISCV_TOOLCHAIN_PATH "riscv32-unknown-elf-gcc" ENV PATH)
+message("RISC-V compiler found in: ${RISCV_TOOLCHAIN_PATH}")
+
+set(CMAKE_SYSTEM_NAME Generic)
+
+set(CMAKE_C_COMPILER ${RISCV_TOOLCHAIN_PATH}/riscv32-unknown-elf-gcc)
+set(CMAKE_CXX_COMPILER ${RISCV_TOOLCHAIN_PATH}/riscv32-unknown-elf-g++)
+
+set(RISCV_GENERAL_COMPILER_FLAGS "-g -nostdlib")
+set(RISCV_C_FLAGS ${RISCV_GENERAL_COMPILER_FLAGS})
+set(RISCV_CXX_FLAGS ${RISCV_GENERAL_COMPILER_FLAGS})
+
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${RISCV_C_FLAGS}")
+set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${RISCV_CXX_FLAGS}")
diff --git a/caravel_firmware/environment/apt_requirements.txt b/caravel_firmware/environment/apt_requirements.txt
new file mode 100644
index 000000000..463a70a72
--- /dev/null
+++ b/caravel_firmware/environment/apt_requirements.txt
@@ -0,0 +1,30 @@
+# Requirements to install with apt
+
+# Shell tools
+bash-completion
+git
+vim
+
+# Firmware build dependencies
+ninja-build
+
+# RISC-V toolchain dependencies
+autoconf
+automake
+autotools-dev
+bc
+bison
+build-essential
+curl
+flex
+gawk
+gperf
+libexpat-dev
+libgmp-dev
+libmpc-dev
+libmpfr-dev
+libtool
+patchutils
+python3
+texinfo
+zlib1g-dev
diff --git a/caravel_firmware/environment/riscv_toolchain.dockerfile b/caravel_firmware/environment/riscv_toolchain.dockerfile
new file mode 100644
index 000000000..909c2416f
--- /dev/null
+++ b/caravel_firmware/environment/riscv_toolchain.dockerfile
@@ -0,0 +1,38 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+ARG BASE_IMAGE=ubuntu:20.04
+FROM ${BASE_IMAGE}
+
+ENV TOOLCHAIN_DOWNLOAD_DIR=/tmp/riscv-gnu-toolchain
+ENV TOOLCHAIN_INSTALL_DIR=/opt/riscv32i
+
+ARG DEBIAN_FRONTEND=noninteractive
+
+COPY ./environment/apt_requirements.txt /tmp
+
+RUN apt-get update && \
+    apt-get install -y $(grep -v "^#" /tmp/apt_requirements.txt | tr "\n" " ")
+
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain ${TOOLCHAIN_DOWNLOAD_DIR} && \
+    cd ${TOOLCHAIN_DOWNLOAD_DIR} && \
+    ./configure --prefix=${TOOLCHAIN_INSTALL_DIR} --with-arch=rv32i && \
+    make -j $(nproc) && \
+    cd / && \
+    rm -rf ${TOOLCHAIN_DOWNLOAD_DIR}
+
+ENV PATH=${TOOLCHAIN_INSTALL_DIR}/bin:${PATH}
+
+CMD /bin/bash
diff --git a/caravel_firmware/include/common.h b/caravel_firmware/include/common.h
new file mode 100644
index 000000000..9fbc7c257
--- /dev/null
+++ b/caravel_firmware/include/common.h
@@ -0,0 +1,254 @@
+#ifndef __HW_COMMON_H
+#define __HW_COMMON_H
+
+#include <stdint.h>
+#include "soc.h"
+// #include "system.h"
+
+/* To overwrite CSR subregister accessors, define extern, non-inlined versions
+ * of csr_[read|write]_simple(), and define CSR_ACCESSORS_DEFINED.
+ */
+
+#ifndef CSR_ACCESSORS_DEFINED
+#define CSR_ACCESSORS_DEFINED
+
+#ifdef __ASSEMBLER__
+#define MMPTR(x) x
+#else /* ! __ASSEMBLER__ */
+
+/* CSRs are stored in subregister slices of CONFIG_CSR_DATA_WIDTH (native
+ * endianness), with the least significant slice at the lowest aligned
+ * (base) address. */
+
+/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t
+ * aligned locations: */
+#define MMPTR(a) (*((volatile uint32_t *)(a)))
+
+static inline void csr_write_simple(unsigned long v, unsigned long a)
+{
+	MMPTR(a) = v;
+}
+
+static inline unsigned long csr_read_simple(unsigned long a)
+{
+	return MMPTR(a);
+}
+
+#endif /* ! __ASSEMBLER__ */
+
+#endif /* ! CSR_ACCESSORS_DEFINED */
+
+/* CSR data width (subreg. width) in bytes, for direct comparson to sizeof() */
+#define CSR_DW_BYTES     (CONFIG_CSR_DATA_WIDTH/8)
+#define CSR_OFFSET_BYTES 4
+
+#ifndef __ASSEMBLER__
+
+/* Number of subregs required for various total byte sizes, by subreg width:
+ * NOTE: 1, 2, 4, and 8 bytes represent uint[8|16|32|64]_t C types; However,
+ *       CSRs of intermediate byte sizes (24, 40, 48, and 56) are NOT padded
+ *       (with extra unallocated subregisters) to the next valid C type!
+ *  +-----+-----------------+
+ *  | csr |      bytes      |
+ *  | _dw | 1 2 3 4 5 6 7 8 |
+ *  |     |-----=---=-=-=---|
+ *  |  1  | 1 2 3 4 5 6 7 8 |
+ *  |  2  | 1 1 2 2 3 3 4 4 |
+ *  |  4  | 1 1 1 1 2 2 2 2 |
+ *  |  8  | 1 1 1 1 1 1 1 1 |
+ *  +-----+-----------------+ */
+static inline int num_subregs(int csr_bytes)
+{
+	return (csr_bytes - 1) / CSR_DW_BYTES + 1;
+}
+
+/* Read a CSR of size 'csr_bytes' located at address 'a'. */
+static inline uint64_t _csr_rd(unsigned long a, int csr_bytes)
+{
+	uint64_t r = csr_read_simple(a);
+	for (int i = 1; i < num_subregs(csr_bytes); i++) {
+		r <<= CONFIG_CSR_DATA_WIDTH;
+		a += CSR_OFFSET_BYTES;
+		r |= csr_read_simple(a);
+	}
+	return r;
+}
+
+/* Write value 'v' to a CSR of size 'csr_bytes' located at address 'a'. */
+static inline void _csr_wr(unsigned long a, uint64_t v, int csr_bytes)
+{
+	int ns = num_subregs(csr_bytes);
+	for (int i = 0; i < ns; i++) {
+		csr_write_simple(v >> (CONFIG_CSR_DATA_WIDTH * (ns - 1 - i)), a);
+		a += CSR_OFFSET_BYTES;
+	}
+}
+
+// FIXME: - should we provide 24, 40, 48, and 56 bit csr_[rd|wr] methods?
+
+static inline uint8_t csr_rd_uint8(unsigned long a)
+{
+	return _csr_rd(a, sizeof(uint8_t));
+}
+
+static inline void csr_wr_uint8(uint8_t v, unsigned long a)
+{
+	_csr_wr(a, v, sizeof(uint8_t));
+}
+
+static inline uint16_t csr_rd_uint16(unsigned long a)
+{
+	return _csr_rd(a, sizeof(uint16_t));
+}
+
+static inline void csr_wr_uint16(uint16_t v, unsigned long a)
+{
+	_csr_wr(a, v, sizeof(uint16_t));
+}
+
+static inline uint32_t csr_rd_uint32(unsigned long a)
+{
+	return _csr_rd(a, sizeof(uint32_t));
+}
+
+static inline void csr_wr_uint32(uint32_t v, unsigned long a)
+{
+	_csr_wr(a, v, sizeof(uint32_t));
+}
+
+static inline uint64_t csr_rd_uint64(unsigned long a)
+{
+	return _csr_rd(a, sizeof(uint64_t));
+}
+
+static inline void csr_wr_uint64(uint64_t v, unsigned long a)
+{
+	_csr_wr(a, v, sizeof(uint64_t));
+}
+
+/* Read a CSR located at address 'a' into an array 'buf' of 'cnt' elements.
+ *
+ * NOTE: Since CSR_DW_BYTES is a constant here, we might be tempted to further
+ * optimize things by leaving out one or the other of the if() branches below,
+ * depending on each unsigned type width;
+ * However, this code is also meant to serve as a reference for how CSRs are
+ * to be manipulated by other programs (e.g., an OS kernel), which may benefit
+ * from dynamically handling multiple possible CSR subregister data widths
+ * (e.g., by passing a value in through the Device Tree).
+ * Ultimately, if CSR_DW_BYTES is indeed a constant, the compiler should be
+ * able to determine on its own whether it can automatically optimize away one
+ * of the if() branches! */
+#define _csr_rd_buf(a, buf, cnt) \
+{ \
+	int i, j, offset, nsubregs, nsubelems; \
+	uint64_t r; \
+	if (sizeof(buf[0]) >= CSR_DW_BYTES) { \
+		/* One or more subregisters per element */ \
+		for (i=0; i<cnt; i++) { \
+			buf[i] = _csr_rd(a, sizeof(buf[0])); \
+			a += CSR_OFFSET_BYTES * num_subregs(sizeof(buf[0])); \
+		} \
+	} else { \
+		/* Multiple elements per subregister (2, 4, or 8) */ \
+		nsubregs  = num_subregs(sizeof(buf[0]) * cnt); \
+		nsubelems = CSR_DW_BYTES / sizeof(buf[0]); \
+		offset    = nsubregs*nsubelems - cnt; \
+		for (i=0; i<nsubregs; i++) { \
+			r = csr_read_simple(a);	\
+			for (j= nsubelems - 1; j >= 0; j--) { \
+				if ((i * nsubelems + j - offset) >= 0) { \
+					buf[i * nsubelems + j - offset] = r; \
+					r >>= sizeof(buf[0]) * 8; \
+				} \
+			} \
+			a += CSR_OFFSET_BYTES;	\
+		} \
+	} \
+}
+
+/* Write an array 'buf' of 'cnt' elements to a CSR located at address 'a'.
+ *
+ * NOTE: The same optimization considerations apply here as with _csr_rd_buf()
+ * above.
+ */
+#define _csr_wr_buf(a, buf, cnt) \
+{ \
+	int i, j, offset, nsubregs, nsubelems; \
+	uint64_t v; \
+	if (sizeof(buf[0]) >= CSR_DW_BYTES) { \
+		/* One or more subregisters per element */ \
+		for (i = 0; i < cnt; i++) { \
+			_csr_wr(a, buf[i], sizeof(buf[0])); \
+			a += CSR_OFFSET_BYTES * num_subregs(sizeof(buf[0])); \
+		} \
+	} else { \
+		/* Multiple elements per subregister (2, 4, or 8) */ \
+		nsubregs  = num_subregs(sizeof(buf[0]) * cnt); \
+		nsubelems = CSR_DW_BYTES / sizeof(buf[0]); \
+		offset    = nsubregs*nsubelems - cnt; \
+		for (i = 0; i < nsubregs; i++) { \
+			v = 0; \
+			for (j= 0; j < nsubelems; j++) { \
+				if ((i * nsubelems + j - offset) >= 0) { \
+					v <<= sizeof(buf[0]) * 8; \
+					v |= buf[i * nsubelems + j - offset]; \
+				} \
+			} \
+			csr_write_simple(v, a); \
+			a += CSR_OFFSET_BYTES;	\
+		} \
+	} \
+}
+
+static inline void csr_rd_buf_uint8(unsigned long a, uint8_t *buf, int cnt)
+{
+	_csr_rd_buf(a, buf, cnt);
+}
+
+static inline void csr_wr_buf_uint8(unsigned long a,
+					const uint8_t *buf, int cnt)
+{
+	_csr_wr_buf(a, buf, cnt);
+}
+
+static inline void csr_rd_buf_uint16(unsigned long a, uint16_t *buf, int cnt)
+{
+	_csr_rd_buf(a, buf, cnt);
+}
+
+static inline void csr_wr_buf_uint16(unsigned long a,
+					const uint16_t *buf, int cnt)
+{
+	_csr_wr_buf(a, buf, cnt);
+}
+
+static inline void csr_rd_buf_uint32(unsigned long a, uint32_t *buf, int cnt)
+{
+	_csr_rd_buf(a, buf, cnt);
+}
+
+static inline void csr_wr_buf_uint32(unsigned long a,
+					const uint32_t *buf, int cnt)
+{
+	_csr_wr_buf(a, buf, cnt);
+}
+
+/* NOTE: the macros' "else" branch is unreachable, no need to be warned
+ * about a >= 64bit left shift! */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wshift-count-overflow"
+static inline void csr_rd_buf_uint64(unsigned long a, uint64_t *buf, int cnt)
+{
+	_csr_rd_buf(a, buf, cnt);
+}
+
+static inline void csr_wr_buf_uint64(unsigned long a,
+					const uint64_t *buf, int cnt)
+{
+	_csr_wr_buf(a, buf, cnt);
+}
+#pragma GCC diagnostic pop
+
+#endif /* ! __ASSEMBLER__ */
+
+#endif /* __HW_COMMON_H */
diff --git a/caravel_firmware/include/csr.h b/caravel_firmware/include/csr.h
new file mode 100644
index 000000000..6f83e89f7
--- /dev/null
+++ b/caravel_firmware/include/csr.h
@@ -0,0 +1,1301 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (9a0be7a) & LiteX (017dfc8) on 2021-12-07 10:21:22
+//--------------------------------------------------------------------------------
+// #include <generated/soc.h>
+#ifndef __GENERATED_CSR_H
+#define __GENERATED_CSR_H
+#include <stdint.h>
+#include "common.h"
+#ifndef CSR_BASE
+#define CSR_BASE 0xf0000000L
+#endif
+
+/* ctrl */
+#define CSR_CTRL_BASE (CSR_BASE + 0x0L)
+#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x0L)
+#define CSR_CTRL_RESET_SIZE 1
+static inline uint32_t ctrl_reset_read(void) {
+	return csr_read_simple(CSR_BASE + 0x0L);
+}
+static inline void ctrl_reset_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x0L);
+}
+#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
+#define CSR_CTRL_RESET_SOC_RST_SIZE 1
+static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t ctrl_reset_soc_rst_read(void) {
+	uint32_t word = ctrl_reset_read();
+	return ctrl_reset_soc_rst_extract(word);
+}
+static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
+	uint32_t oldword = ctrl_reset_read();
+	uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
+	ctrl_reset_write(newword);
+}
+#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
+#define CSR_CTRL_RESET_CPU_RST_SIZE 1
+static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t ctrl_reset_cpu_rst_read(void) {
+	uint32_t word = ctrl_reset_read();
+	return ctrl_reset_cpu_rst_extract(word);
+}
+static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
+	uint32_t oldword = ctrl_reset_read();
+	uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
+	ctrl_reset_write(newword);
+}
+#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x4L)
+#define CSR_CTRL_SCRATCH_SIZE 1
+static inline uint32_t ctrl_scratch_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4L);
+}
+static inline void ctrl_scratch_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4L);
+}
+#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x8L)
+#define CSR_CTRL_BUS_ERRORS_SIZE 1
+static inline uint32_t ctrl_bus_errors_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8L);
+}
+
+/* debug_mode */
+#define CSR_DEBUG_MODE_BASE (CSR_BASE + 0x800L)
+#define CSR_DEBUG_MODE_OUT_ADDR (CSR_BASE + 0x800L)
+#define CSR_DEBUG_MODE_OUT_SIZE 1
+static inline uint32_t debug_mode_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x800L);
+}
+static inline void debug_mode_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x800L);
+}
+
+/* debug_oeb */
+#define CSR_DEBUG_OEB_BASE (CSR_BASE + 0x1000L)
+#define CSR_DEBUG_OEB_OUT_ADDR (CSR_BASE + 0x1000L)
+#define CSR_DEBUG_OEB_OUT_SIZE 1
+static inline uint32_t debug_oeb_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1000L);
+}
+static inline void debug_oeb_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1000L);
+}
+
+/* flash_core */
+#define CSR_FLASH_CORE_BASE (CSR_BASE + 0x1800L)
+#define CSR_FLASH_CORE_MMAP_DUMMY_BITS_ADDR (CSR_BASE + 0x1800L)
+#define CSR_FLASH_CORE_MMAP_DUMMY_BITS_SIZE 1
+static inline uint32_t flash_core_mmap_dummy_bits_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1800L);
+}
+static inline void flash_core_mmap_dummy_bits_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1800L);
+}
+#define CSR_FLASH_CORE_MASTER_CS_ADDR (CSR_BASE + 0x1804L)
+#define CSR_FLASH_CORE_MASTER_CS_SIZE 1
+static inline uint32_t flash_core_master_cs_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1804L);
+}
+static inline void flash_core_master_cs_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1804L);
+}
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_ADDR (CSR_BASE + 0x1808L)
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_SIZE 1
+static inline uint32_t flash_core_master_phyconfig_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1808L);
+}
+static inline void flash_core_master_phyconfig_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1808L);
+}
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET 0
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_LEN_SIZE 8
+static inline uint32_t flash_core_master_phyconfig_len_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 8)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t flash_core_master_phyconfig_len_read(void) {
+	uint32_t word = flash_core_master_phyconfig_read();
+	return flash_core_master_phyconfig_len_extract(word);
+}
+static inline uint32_t flash_core_master_phyconfig_len_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 8)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void flash_core_master_phyconfig_len_write(uint32_t plain_value) {
+	uint32_t oldword = flash_core_master_phyconfig_read();
+	uint32_t newword = flash_core_master_phyconfig_len_replace(oldword, plain_value);
+	flash_core_master_phyconfig_write(newword);
+}
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 8
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_WIDTH_SIZE 4
+static inline uint32_t flash_core_master_phyconfig_width_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 4)-1);
+	return ( (oldword >> 8) & mask );
+}
+static inline uint32_t flash_core_master_phyconfig_width_read(void) {
+	uint32_t word = flash_core_master_phyconfig_read();
+	return flash_core_master_phyconfig_width_extract(word);
+}
+static inline uint32_t flash_core_master_phyconfig_width_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 4)-1);
+	return (oldword & (~(mask << 8))) | (mask & plain_value)<< 8 ;
+}
+static inline void flash_core_master_phyconfig_width_write(uint32_t plain_value) {
+	uint32_t oldword = flash_core_master_phyconfig_read();
+	uint32_t newword = flash_core_master_phyconfig_width_replace(oldword, plain_value);
+	flash_core_master_phyconfig_write(newword);
+}
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET 16
+#define CSR_FLASH_CORE_MASTER_PHYCONFIG_MASK_SIZE 8
+static inline uint32_t flash_core_master_phyconfig_mask_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 8)-1);
+	return ( (oldword >> 16) & mask );
+}
+static inline uint32_t flash_core_master_phyconfig_mask_read(void) {
+	uint32_t word = flash_core_master_phyconfig_read();
+	return flash_core_master_phyconfig_mask_extract(word);
+}
+static inline uint32_t flash_core_master_phyconfig_mask_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 8)-1);
+	return (oldword & (~(mask << 16))) | (mask & plain_value)<< 16 ;
+}
+static inline void flash_core_master_phyconfig_mask_write(uint32_t plain_value) {
+	uint32_t oldword = flash_core_master_phyconfig_read();
+	uint32_t newword = flash_core_master_phyconfig_mask_replace(oldword, plain_value);
+	flash_core_master_phyconfig_write(newword);
+}
+#define CSR_FLASH_CORE_MASTER_RXTX_ADDR (CSR_BASE + 0x180cL)
+#define CSR_FLASH_CORE_MASTER_RXTX_SIZE 1
+static inline uint32_t flash_core_master_rxtx_read(void) {
+	return csr_read_simple(CSR_BASE + 0x180cL);
+}
+static inline void flash_core_master_rxtx_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x180cL);
+}
+#define CSR_FLASH_CORE_MASTER_STATUS_ADDR (CSR_BASE + 0x1810L)
+#define CSR_FLASH_CORE_MASTER_STATUS_SIZE 1
+static inline uint32_t flash_core_master_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1810L);
+}
+#define CSR_FLASH_CORE_MASTER_STATUS_TX_READY_OFFSET 0
+#define CSR_FLASH_CORE_MASTER_STATUS_TX_READY_SIZE 1
+static inline uint32_t flash_core_master_status_tx_ready_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t flash_core_master_status_tx_ready_read(void) {
+	uint32_t word = flash_core_master_status_read();
+	return flash_core_master_status_tx_ready_extract(word);
+}
+#define CSR_FLASH_CORE_MASTER_STATUS_RX_READY_OFFSET 1
+#define CSR_FLASH_CORE_MASTER_STATUS_RX_READY_SIZE 1
+static inline uint32_t flash_core_master_status_rx_ready_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t flash_core_master_status_rx_ready_read(void) {
+	uint32_t word = flash_core_master_status_read();
+	return flash_core_master_status_rx_ready_extract(word);
+}
+
+/* flash_phy */
+#define CSR_FLASH_PHY_BASE (CSR_BASE + 0x2000L)
+#define CSR_FLASH_PHY_CLK_DIVISOR_ADDR (CSR_BASE + 0x2000L)
+#define CSR_FLASH_PHY_CLK_DIVISOR_SIZE 1
+static inline uint32_t flash_phy_clk_divisor_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2000L);
+}
+static inline void flash_phy_clk_divisor_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2000L);
+}
+
+/* gpio */
+#define CSR_GPIO_BASE (CSR_BASE + 0x2800L)
+#define CSR_GPIO_MODE1_ADDR (CSR_BASE + 0x2800L)
+#define CSR_GPIO_MODE1_SIZE 1
+static inline uint32_t gpio_mode1_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2800L);
+}
+static inline void gpio_mode1_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2800L);
+}
+#define CSR_GPIO_MODE0_ADDR (CSR_BASE + 0x2804L)
+#define CSR_GPIO_MODE0_SIZE 1
+static inline uint32_t gpio_mode0_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2804L);
+}
+static inline void gpio_mode0_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2804L);
+}
+#define CSR_GPIO_IEN_ADDR (CSR_BASE + 0x2808L)
+#define CSR_GPIO_IEN_SIZE 1
+static inline uint32_t gpio_ien_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2808L);
+}
+static inline void gpio_ien_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2808L);
+}
+#define CSR_GPIO_OE_ADDR (CSR_BASE + 0x280cL)
+#define CSR_GPIO_OE_SIZE 1
+static inline uint32_t gpio_oe_read(void) {
+	return csr_read_simple(CSR_BASE + 0x280cL);
+}
+static inline void gpio_oe_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x280cL);
+}
+#define CSR_GPIO_IN_ADDR (CSR_BASE + 0x2810L)
+#define CSR_GPIO_IN_SIZE 1
+static inline uint32_t gpio_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2810L);
+}
+#define CSR_GPIO_OUT_ADDR (CSR_BASE + 0x2814L)
+#define CSR_GPIO_OUT_SIZE 1
+static inline uint32_t gpio_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2814L);
+}
+static inline void gpio_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2814L);
+}
+
+/* la */
+#define CSR_LA_BASE (CSR_BASE + 0x3000L)
+#define CSR_LA_IEN_ADDR (CSR_BASE + 0x3000L)
+#define CSR_LA_IEN_SIZE 4
+#define CSR_LA_OE_ADDR (CSR_BASE + 0x3010L)
+#define CSR_LA_OE_SIZE 4
+#define CSR_LA_IN_ADDR (CSR_BASE + 0x3020L)
+#define CSR_LA_IN_SIZE 4
+#define CSR_LA_OUT_ADDR (CSR_BASE + 0x3030L)
+#define CSR_LA_OUT_SIZE 4
+
+/* mprj_wb_iena */
+#define CSR_MPRJ_WB_IENA_BASE (CSR_BASE + 0x3800L)
+#define CSR_MPRJ_WB_IENA_OUT_ADDR (CSR_BASE + 0x3800L)
+#define CSR_MPRJ_WB_IENA_OUT_SIZE 1
+static inline uint32_t mprj_wb_iena_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x3800L);
+}
+static inline void mprj_wb_iena_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x3800L);
+}
+
+/* spi_enabled */
+#define CSR_SPI_ENABLED_BASE (CSR_BASE + 0x4000L)
+#define CSR_SPI_ENABLED_OUT_ADDR (CSR_BASE + 0x4000L)
+#define CSR_SPI_ENABLED_OUT_SIZE 1
+static inline uint32_t spi_enabled_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4000L);
+}
+static inline void spi_enabled_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4000L);
+}
+
+/* spi_master */
+#define CSR_SPI_MASTER_BASE (CSR_BASE + 0x4800L)
+#define CSR_SPI_MASTER_CONTROL_ADDR (CSR_BASE + 0x4800L)
+#define CSR_SPI_MASTER_CONTROL_SIZE 1
+static inline uint32_t spi_master_control_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4800L);
+}
+static inline void spi_master_control_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4800L);
+}
+#define CSR_SPI_MASTER_CONTROL_START_OFFSET 0
+#define CSR_SPI_MASTER_CONTROL_START_SIZE 1
+static inline uint32_t spi_master_control_start_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t spi_master_control_start_read(void) {
+	uint32_t word = spi_master_control_read();
+	return spi_master_control_start_extract(word);
+}
+static inline uint32_t spi_master_control_start_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void spi_master_control_start_write(uint32_t plain_value) {
+	uint32_t oldword = spi_master_control_read();
+	uint32_t newword = spi_master_control_start_replace(oldword, plain_value);
+	spi_master_control_write(newword);
+}
+#define CSR_SPI_MASTER_CONTROL_LENGTH_OFFSET 8
+#define CSR_SPI_MASTER_CONTROL_LENGTH_SIZE 8
+static inline uint32_t spi_master_control_length_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 8)-1);
+	return ( (oldword >> 8) & mask );
+}
+static inline uint32_t spi_master_control_length_read(void) {
+	uint32_t word = spi_master_control_read();
+	return spi_master_control_length_extract(word);
+}
+static inline uint32_t spi_master_control_length_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 8)-1);
+	return (oldword & (~(mask << 8))) | (mask & plain_value)<< 8 ;
+}
+static inline void spi_master_control_length_write(uint32_t plain_value) {
+	uint32_t oldword = spi_master_control_read();
+	uint32_t newword = spi_master_control_length_replace(oldword, plain_value);
+	spi_master_control_write(newword);
+}
+#define CSR_SPI_MASTER_STATUS_ADDR (CSR_BASE + 0x4804L)
+#define CSR_SPI_MASTER_STATUS_SIZE 1
+static inline uint32_t spi_master_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4804L);
+}
+#define CSR_SPI_MASTER_STATUS_DONE_OFFSET 0
+#define CSR_SPI_MASTER_STATUS_DONE_SIZE 1
+static inline uint32_t spi_master_status_done_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t spi_master_status_done_read(void) {
+	uint32_t word = spi_master_status_read();
+	return spi_master_status_done_extract(word);
+}
+#define CSR_SPI_MASTER_MOSI_ADDR (CSR_BASE + 0x4808L)
+#define CSR_SPI_MASTER_MOSI_SIZE 1
+static inline uint32_t spi_master_mosi_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4808L);
+}
+static inline void spi_master_mosi_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4808L);
+}
+#define CSR_SPI_MASTER_MISO_ADDR (CSR_BASE + 0x480cL)
+#define CSR_SPI_MASTER_MISO_SIZE 1
+static inline uint32_t spi_master_miso_read(void) {
+	return csr_read_simple(CSR_BASE + 0x480cL);
+}
+#define CSR_SPI_MASTER_CS_ADDR (CSR_BASE + 0x4810L)
+#define CSR_SPI_MASTER_CS_SIZE 1
+static inline uint32_t spi_master_cs_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4810L);
+}
+static inline void spi_master_cs_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4810L);
+}
+#define CSR_SPI_MASTER_CS_SEL_OFFSET 0
+#define CSR_SPI_MASTER_CS_SEL_SIZE 1
+static inline uint32_t spi_master_cs_sel_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t spi_master_cs_sel_read(void) {
+	uint32_t word = spi_master_cs_read();
+	return spi_master_cs_sel_extract(word);
+}
+static inline uint32_t spi_master_cs_sel_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void spi_master_cs_sel_write(uint32_t plain_value) {
+	uint32_t oldword = spi_master_cs_read();
+	uint32_t newword = spi_master_cs_sel_replace(oldword, plain_value);
+	spi_master_cs_write(newword);
+}
+#define CSR_SPI_MASTER_CS_MODE_OFFSET 16
+#define CSR_SPI_MASTER_CS_MODE_SIZE 1
+static inline uint32_t spi_master_cs_mode_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 16) & mask );
+}
+static inline uint32_t spi_master_cs_mode_read(void) {
+	uint32_t word = spi_master_cs_read();
+	return spi_master_cs_mode_extract(word);
+}
+static inline uint32_t spi_master_cs_mode_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 16))) | (mask & plain_value)<< 16 ;
+}
+static inline void spi_master_cs_mode_write(uint32_t plain_value) {
+	uint32_t oldword = spi_master_cs_read();
+	uint32_t newword = spi_master_cs_mode_replace(oldword, plain_value);
+	spi_master_cs_write(newword);
+}
+#define CSR_SPI_MASTER_LOOPBACK_ADDR (CSR_BASE + 0x4814L)
+#define CSR_SPI_MASTER_LOOPBACK_SIZE 1
+static inline uint32_t spi_master_loopback_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4814L);
+}
+static inline void spi_master_loopback_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4814L);
+}
+#define CSR_SPI_MASTER_LOOPBACK_MODE_OFFSET 0
+#define CSR_SPI_MASTER_LOOPBACK_MODE_SIZE 1
+static inline uint32_t spi_master_loopback_mode_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t spi_master_loopback_mode_read(void) {
+	uint32_t word = spi_master_loopback_read();
+	return spi_master_loopback_mode_extract(word);
+}
+static inline uint32_t spi_master_loopback_mode_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void spi_master_loopback_mode_write(uint32_t plain_value) {
+	uint32_t oldword = spi_master_loopback_read();
+	uint32_t newword = spi_master_loopback_mode_replace(oldword, plain_value);
+	spi_master_loopback_write(newword);
+}
+#define CSR_SPI_MASTER_CLK_DIVIDER_ADDR (CSR_BASE + 0x4818L)
+#define CSR_SPI_MASTER_CLK_DIVIDER_SIZE 1
+static inline uint32_t spi_master_clk_divider_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4818L);
+}
+static inline void spi_master_clk_divider_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4818L);
+}
+
+/* timer0 */
+#define CSR_TIMER0_BASE (CSR_BASE + 0x5000L)
+#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x5000L)
+#define CSR_TIMER0_LOAD_SIZE 1
+static inline uint32_t timer0_load_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5000L);
+}
+static inline void timer0_load_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5000L);
+}
+#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x5004L)
+#define CSR_TIMER0_RELOAD_SIZE 1
+static inline uint32_t timer0_reload_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5004L);
+}
+static inline void timer0_reload_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5004L);
+}
+#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x5008L)
+#define CSR_TIMER0_EN_SIZE 1
+static inline uint32_t timer0_en_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5008L);
+}
+static inline void timer0_en_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5008L);
+}
+#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x500cL)
+#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
+static inline uint32_t timer0_update_value_read(void) {
+	return csr_read_simple(CSR_BASE + 0x500cL);
+}
+static inline void timer0_update_value_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x500cL);
+}
+#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x5010L)
+#define CSR_TIMER0_VALUE_SIZE 1
+static inline uint32_t timer0_value_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5010L);
+}
+#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x5014L)
+#define CSR_TIMER0_EV_STATUS_SIZE 1
+static inline uint32_t timer0_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5014L);
+}
+#define CSR_TIMER0_EV_STATUS_ZERO_OFFSET 0
+#define CSR_TIMER0_EV_STATUS_ZERO_SIZE 1
+static inline uint32_t timer0_ev_status_zero_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t timer0_ev_status_zero_read(void) {
+	uint32_t word = timer0_ev_status_read();
+	return timer0_ev_status_zero_extract(word);
+}
+#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x5018L)
+#define CSR_TIMER0_EV_PENDING_SIZE 1
+static inline uint32_t timer0_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5018L);
+}
+static inline void timer0_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5018L);
+}
+#define CSR_TIMER0_EV_PENDING_ZERO_OFFSET 0
+#define CSR_TIMER0_EV_PENDING_ZERO_SIZE 1
+static inline uint32_t timer0_ev_pending_zero_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t timer0_ev_pending_zero_read(void) {
+	uint32_t word = timer0_ev_pending_read();
+	return timer0_ev_pending_zero_extract(word);
+}
+static inline uint32_t timer0_ev_pending_zero_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void timer0_ev_pending_zero_write(uint32_t plain_value) {
+	uint32_t oldword = timer0_ev_pending_read();
+	uint32_t newword = timer0_ev_pending_zero_replace(oldword, plain_value);
+	timer0_ev_pending_write(newword);
+}
+#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x501cL)
+#define CSR_TIMER0_EV_ENABLE_SIZE 1
+static inline uint32_t timer0_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x501cL);
+}
+static inline void timer0_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x501cL);
+}
+#define CSR_TIMER0_EV_ENABLE_ZERO_OFFSET 0
+#define CSR_TIMER0_EV_ENABLE_ZERO_SIZE 1
+static inline uint32_t timer0_ev_enable_zero_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t timer0_ev_enable_zero_read(void) {
+	uint32_t word = timer0_ev_enable_read();
+	return timer0_ev_enable_zero_extract(word);
+}
+static inline uint32_t timer0_ev_enable_zero_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void timer0_ev_enable_zero_write(uint32_t plain_value) {
+	uint32_t oldword = timer0_ev_enable_read();
+	uint32_t newword = timer0_ev_enable_zero_replace(oldword, plain_value);
+	timer0_ev_enable_write(newword);
+}
+
+/* uart */
+#define CSR_UART_BASE (CSR_BASE + 0x5800L)
+#define CSR_UART_RXTX_ADDR (CSR_BASE + 0x5800L)
+#define CSR_UART_RXTX_SIZE 1
+static inline uint32_t uart_rxtx_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5800L);
+}
+static inline void uart_rxtx_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5800L);
+}
+#define CSR_UART_TXFULL_ADDR (CSR_BASE + 0x5804L)
+#define CSR_UART_TXFULL_SIZE 1
+static inline uint32_t uart_txfull_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5804L);
+}
+#define CSR_UART_RXEMPTY_ADDR (CSR_BASE + 0x5808L)
+#define CSR_UART_RXEMPTY_SIZE 1
+static inline uint32_t uart_rxempty_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5808L);
+}
+#define CSR_UART_EV_STATUS_ADDR (CSR_BASE + 0x580cL)
+#define CSR_UART_EV_STATUS_SIZE 1
+static inline uint32_t uart_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x580cL);
+}
+#define CSR_UART_EV_STATUS_TX_OFFSET 0
+#define CSR_UART_EV_STATUS_TX_SIZE 1
+static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_ev_status_tx_read(void) {
+	uint32_t word = uart_ev_status_read();
+	return uart_ev_status_tx_extract(word);
+}
+#define CSR_UART_EV_STATUS_RX_OFFSET 1
+#define CSR_UART_EV_STATUS_RX_SIZE 1
+static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_ev_status_rx_read(void) {
+	uint32_t word = uart_ev_status_read();
+	return uart_ev_status_rx_extract(word);
+}
+#define CSR_UART_EV_PENDING_ADDR (CSR_BASE + 0x5810L)
+#define CSR_UART_EV_PENDING_SIZE 1
+static inline uint32_t uart_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5810L);
+}
+static inline void uart_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5810L);
+}
+#define CSR_UART_EV_PENDING_TX_OFFSET 0
+#define CSR_UART_EV_PENDING_TX_SIZE 1
+static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_ev_pending_tx_read(void) {
+	uint32_t word = uart_ev_pending_read();
+	return uart_ev_pending_tx_extract(word);
+}
+static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void uart_ev_pending_tx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_ev_pending_read();
+	uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value);
+	uart_ev_pending_write(newword);
+}
+#define CSR_UART_EV_PENDING_RX_OFFSET 1
+#define CSR_UART_EV_PENDING_RX_SIZE 1
+static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_ev_pending_rx_read(void) {
+	uint32_t word = uart_ev_pending_read();
+	return uart_ev_pending_rx_extract(word);
+}
+static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void uart_ev_pending_rx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_ev_pending_read();
+	uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value);
+	uart_ev_pending_write(newword);
+}
+#define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x5814L)
+#define CSR_UART_EV_ENABLE_SIZE 1
+static inline uint32_t uart_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5814L);
+}
+static inline void uart_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x5814L);
+}
+#define CSR_UART_EV_ENABLE_TX_OFFSET 0
+#define CSR_UART_EV_ENABLE_TX_SIZE 1
+static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_ev_enable_tx_read(void) {
+	uint32_t word = uart_ev_enable_read();
+	return uart_ev_enable_tx_extract(word);
+}
+static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void uart_ev_enable_tx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_ev_enable_read();
+	uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value);
+	uart_ev_enable_write(newword);
+}
+#define CSR_UART_EV_ENABLE_RX_OFFSET 1
+#define CSR_UART_EV_ENABLE_RX_SIZE 1
+static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_ev_enable_rx_read(void) {
+	uint32_t word = uart_ev_enable_read();
+	return uart_ev_enable_rx_extract(word);
+}
+static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void uart_ev_enable_rx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_ev_enable_read();
+	uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value);
+	uart_ev_enable_write(newword);
+}
+#define CSR_UART_TXEMPTY_ADDR (CSR_BASE + 0x5818L)
+#define CSR_UART_TXEMPTY_SIZE 1
+static inline uint32_t uart_txempty_read(void) {
+	return csr_read_simple(CSR_BASE + 0x5818L);
+}
+#define CSR_UART_RXFULL_ADDR (CSR_BASE + 0x581cL)
+#define CSR_UART_RXFULL_SIZE 1
+static inline uint32_t uart_rxfull_read(void) {
+	return csr_read_simple(CSR_BASE + 0x581cL);
+}
+
+/* uart_enabled */
+#define CSR_UART_ENABLED_BASE (CSR_BASE + 0x6000L)
+#define CSR_UART_ENABLED_OUT_ADDR (CSR_BASE + 0x6000L)
+#define CSR_UART_ENABLED_OUT_SIZE 1
+static inline uint32_t uart_enabled_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x6000L);
+}
+static inline void uart_enabled_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x6000L);
+}
+
+/* user_irq_0 */
+#define CSR_USER_IRQ_0_BASE (CSR_BASE + 0x6800L)
+#define CSR_USER_IRQ_0_IN_ADDR (CSR_BASE + 0x6800L)
+#define CSR_USER_IRQ_0_IN_SIZE 1
+static inline uint32_t user_irq_0_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x6800L);
+}
+#define CSR_USER_IRQ_0_MODE_ADDR (CSR_BASE + 0x6804L)
+#define CSR_USER_IRQ_0_MODE_SIZE 1
+static inline uint32_t user_irq_0_mode_read(void) {
+	return csr_read_simple(CSR_BASE + 0x6804L);
+}
+static inline void user_irq_0_mode_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x6804L);
+}
+#define CSR_USER_IRQ_0_EDGE_ADDR (CSR_BASE + 0x6808L)
+#define CSR_USER_IRQ_0_EDGE_SIZE 1
+static inline uint32_t user_irq_0_edge_read(void) {
+	return csr_read_simple(CSR_BASE + 0x6808L);
+}
+static inline void user_irq_0_edge_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x6808L);
+}
+#define CSR_USER_IRQ_0_EV_STATUS_ADDR (CSR_BASE + 0x680cL)
+#define CSR_USER_IRQ_0_EV_STATUS_SIZE 1
+static inline uint32_t user_irq_0_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x680cL);
+}
+#define CSR_USER_IRQ_0_EV_STATUS_I0_OFFSET 0
+#define CSR_USER_IRQ_0_EV_STATUS_I0_SIZE 1
+static inline uint32_t user_irq_0_ev_status_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_0_ev_status_i0_read(void) {
+	uint32_t word = user_irq_0_ev_status_read();
+	return user_irq_0_ev_status_i0_extract(word);
+}
+#define CSR_USER_IRQ_0_EV_PENDING_ADDR (CSR_BASE + 0x6810L)
+#define CSR_USER_IRQ_0_EV_PENDING_SIZE 1
+static inline uint32_t user_irq_0_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x6810L);
+}
+static inline void user_irq_0_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x6810L);
+}
+#define CSR_USER_IRQ_0_EV_PENDING_I0_OFFSET 0
+#define CSR_USER_IRQ_0_EV_PENDING_I0_SIZE 1
+static inline uint32_t user_irq_0_ev_pending_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_0_ev_pending_i0_read(void) {
+	uint32_t word = user_irq_0_ev_pending_read();
+	return user_irq_0_ev_pending_i0_extract(word);
+}
+static inline uint32_t user_irq_0_ev_pending_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_0_ev_pending_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_0_ev_pending_read();
+	uint32_t newword = user_irq_0_ev_pending_i0_replace(oldword, plain_value);
+	user_irq_0_ev_pending_write(newword);
+}
+#define CSR_USER_IRQ_0_EV_ENABLE_ADDR (CSR_BASE + 0x6814L)
+#define CSR_USER_IRQ_0_EV_ENABLE_SIZE 1
+static inline uint32_t user_irq_0_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x6814L);
+}
+static inline void user_irq_0_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x6814L);
+}
+#define CSR_USER_IRQ_0_EV_ENABLE_I0_OFFSET 0
+#define CSR_USER_IRQ_0_EV_ENABLE_I0_SIZE 1
+static inline uint32_t user_irq_0_ev_enable_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_0_ev_enable_i0_read(void) {
+	uint32_t word = user_irq_0_ev_enable_read();
+	return user_irq_0_ev_enable_i0_extract(word);
+}
+static inline uint32_t user_irq_0_ev_enable_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_0_ev_enable_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_0_ev_enable_read();
+	uint32_t newword = user_irq_0_ev_enable_i0_replace(oldword, plain_value);
+	user_irq_0_ev_enable_write(newword);
+}
+
+/* user_irq_1 */
+#define CSR_USER_IRQ_1_BASE (CSR_BASE + 0x7000L)
+#define CSR_USER_IRQ_1_IN_ADDR (CSR_BASE + 0x7000L)
+#define CSR_USER_IRQ_1_IN_SIZE 1
+static inline uint32_t user_irq_1_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7000L);
+}
+#define CSR_USER_IRQ_1_MODE_ADDR (CSR_BASE + 0x7004L)
+#define CSR_USER_IRQ_1_MODE_SIZE 1
+static inline uint32_t user_irq_1_mode_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7004L);
+}
+static inline void user_irq_1_mode_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7004L);
+}
+#define CSR_USER_IRQ_1_EDGE_ADDR (CSR_BASE + 0x7008L)
+#define CSR_USER_IRQ_1_EDGE_SIZE 1
+static inline uint32_t user_irq_1_edge_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7008L);
+}
+static inline void user_irq_1_edge_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7008L);
+}
+#define CSR_USER_IRQ_1_EV_STATUS_ADDR (CSR_BASE + 0x700cL)
+#define CSR_USER_IRQ_1_EV_STATUS_SIZE 1
+static inline uint32_t user_irq_1_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x700cL);
+}
+#define CSR_USER_IRQ_1_EV_STATUS_I0_OFFSET 0
+#define CSR_USER_IRQ_1_EV_STATUS_I0_SIZE 1
+static inline uint32_t user_irq_1_ev_status_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_1_ev_status_i0_read(void) {
+	uint32_t word = user_irq_1_ev_status_read();
+	return user_irq_1_ev_status_i0_extract(word);
+}
+#define CSR_USER_IRQ_1_EV_PENDING_ADDR (CSR_BASE + 0x7010L)
+#define CSR_USER_IRQ_1_EV_PENDING_SIZE 1
+static inline uint32_t user_irq_1_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7010L);
+}
+static inline void user_irq_1_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7010L);
+}
+#define CSR_USER_IRQ_1_EV_PENDING_I0_OFFSET 0
+#define CSR_USER_IRQ_1_EV_PENDING_I0_SIZE 1
+static inline uint32_t user_irq_1_ev_pending_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_1_ev_pending_i0_read(void) {
+	uint32_t word = user_irq_1_ev_pending_read();
+	return user_irq_1_ev_pending_i0_extract(word);
+}
+static inline uint32_t user_irq_1_ev_pending_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_1_ev_pending_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_1_ev_pending_read();
+	uint32_t newword = user_irq_1_ev_pending_i0_replace(oldword, plain_value);
+	user_irq_1_ev_pending_write(newword);
+}
+#define CSR_USER_IRQ_1_EV_ENABLE_ADDR (CSR_BASE + 0x7014L)
+#define CSR_USER_IRQ_1_EV_ENABLE_SIZE 1
+static inline uint32_t user_irq_1_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7014L);
+}
+static inline void user_irq_1_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7014L);
+}
+#define CSR_USER_IRQ_1_EV_ENABLE_I0_OFFSET 0
+#define CSR_USER_IRQ_1_EV_ENABLE_I0_SIZE 1
+static inline uint32_t user_irq_1_ev_enable_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_1_ev_enable_i0_read(void) {
+	uint32_t word = user_irq_1_ev_enable_read();
+	return user_irq_1_ev_enable_i0_extract(word);
+}
+static inline uint32_t user_irq_1_ev_enable_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_1_ev_enable_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_1_ev_enable_read();
+	uint32_t newword = user_irq_1_ev_enable_i0_replace(oldword, plain_value);
+	user_irq_1_ev_enable_write(newword);
+}
+
+/* user_irq_2 */
+#define CSR_USER_IRQ_2_BASE (CSR_BASE + 0x7800L)
+#define CSR_USER_IRQ_2_IN_ADDR (CSR_BASE + 0x7800L)
+#define CSR_USER_IRQ_2_IN_SIZE 1
+static inline uint32_t user_irq_2_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7800L);
+}
+#define CSR_USER_IRQ_2_MODE_ADDR (CSR_BASE + 0x7804L)
+#define CSR_USER_IRQ_2_MODE_SIZE 1
+static inline uint32_t user_irq_2_mode_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7804L);
+}
+static inline void user_irq_2_mode_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7804L);
+}
+#define CSR_USER_IRQ_2_EDGE_ADDR (CSR_BASE + 0x7808L)
+#define CSR_USER_IRQ_2_EDGE_SIZE 1
+static inline uint32_t user_irq_2_edge_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7808L);
+}
+static inline void user_irq_2_edge_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7808L);
+}
+#define CSR_USER_IRQ_2_EV_STATUS_ADDR (CSR_BASE + 0x780cL)
+#define CSR_USER_IRQ_2_EV_STATUS_SIZE 1
+static inline uint32_t user_irq_2_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x780cL);
+}
+#define CSR_USER_IRQ_2_EV_STATUS_I0_OFFSET 0
+#define CSR_USER_IRQ_2_EV_STATUS_I0_SIZE 1
+static inline uint32_t user_irq_2_ev_status_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_2_ev_status_i0_read(void) {
+	uint32_t word = user_irq_2_ev_status_read();
+	return user_irq_2_ev_status_i0_extract(word);
+}
+#define CSR_USER_IRQ_2_EV_PENDING_ADDR (CSR_BASE + 0x7810L)
+#define CSR_USER_IRQ_2_EV_PENDING_SIZE 1
+static inline uint32_t user_irq_2_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7810L);
+}
+static inline void user_irq_2_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7810L);
+}
+#define CSR_USER_IRQ_2_EV_PENDING_I0_OFFSET 0
+#define CSR_USER_IRQ_2_EV_PENDING_I0_SIZE 1
+static inline uint32_t user_irq_2_ev_pending_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_2_ev_pending_i0_read(void) {
+	uint32_t word = user_irq_2_ev_pending_read();
+	return user_irq_2_ev_pending_i0_extract(word);
+}
+static inline uint32_t user_irq_2_ev_pending_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_2_ev_pending_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_2_ev_pending_read();
+	uint32_t newword = user_irq_2_ev_pending_i0_replace(oldword, plain_value);
+	user_irq_2_ev_pending_write(newword);
+}
+#define CSR_USER_IRQ_2_EV_ENABLE_ADDR (CSR_BASE + 0x7814L)
+#define CSR_USER_IRQ_2_EV_ENABLE_SIZE 1
+static inline uint32_t user_irq_2_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x7814L);
+}
+static inline void user_irq_2_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x7814L);
+}
+#define CSR_USER_IRQ_2_EV_ENABLE_I0_OFFSET 0
+#define CSR_USER_IRQ_2_EV_ENABLE_I0_SIZE 1
+static inline uint32_t user_irq_2_ev_enable_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_2_ev_enable_i0_read(void) {
+	uint32_t word = user_irq_2_ev_enable_read();
+	return user_irq_2_ev_enable_i0_extract(word);
+}
+static inline uint32_t user_irq_2_ev_enable_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_2_ev_enable_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_2_ev_enable_read();
+	uint32_t newword = user_irq_2_ev_enable_i0_replace(oldword, plain_value);
+	user_irq_2_ev_enable_write(newword);
+}
+
+/* user_irq_3 */
+#define CSR_USER_IRQ_3_BASE (CSR_BASE + 0x8000L)
+#define CSR_USER_IRQ_3_IN_ADDR (CSR_BASE + 0x8000L)
+#define CSR_USER_IRQ_3_IN_SIZE 1
+static inline uint32_t user_irq_3_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8000L);
+}
+#define CSR_USER_IRQ_3_MODE_ADDR (CSR_BASE + 0x8004L)
+#define CSR_USER_IRQ_3_MODE_SIZE 1
+static inline uint32_t user_irq_3_mode_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8004L);
+}
+static inline void user_irq_3_mode_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8004L);
+}
+#define CSR_USER_IRQ_3_EDGE_ADDR (CSR_BASE + 0x8008L)
+#define CSR_USER_IRQ_3_EDGE_SIZE 1
+static inline uint32_t user_irq_3_edge_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8008L);
+}
+static inline void user_irq_3_edge_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8008L);
+}
+#define CSR_USER_IRQ_3_EV_STATUS_ADDR (CSR_BASE + 0x800cL)
+#define CSR_USER_IRQ_3_EV_STATUS_SIZE 1
+static inline uint32_t user_irq_3_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x800cL);
+}
+#define CSR_USER_IRQ_3_EV_STATUS_I0_OFFSET 0
+#define CSR_USER_IRQ_3_EV_STATUS_I0_SIZE 1
+static inline uint32_t user_irq_3_ev_status_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_3_ev_status_i0_read(void) {
+	uint32_t word = user_irq_3_ev_status_read();
+	return user_irq_3_ev_status_i0_extract(word);
+}
+#define CSR_USER_IRQ_3_EV_PENDING_ADDR (CSR_BASE + 0x8010L)
+#define CSR_USER_IRQ_3_EV_PENDING_SIZE 1
+static inline uint32_t user_irq_3_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8010L);
+}
+static inline void user_irq_3_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8010L);
+}
+#define CSR_USER_IRQ_3_EV_PENDING_I0_OFFSET 0
+#define CSR_USER_IRQ_3_EV_PENDING_I0_SIZE 1
+static inline uint32_t user_irq_3_ev_pending_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_3_ev_pending_i0_read(void) {
+	uint32_t word = user_irq_3_ev_pending_read();
+	return user_irq_3_ev_pending_i0_extract(word);
+}
+static inline uint32_t user_irq_3_ev_pending_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_3_ev_pending_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_3_ev_pending_read();
+	uint32_t newword = user_irq_3_ev_pending_i0_replace(oldword, plain_value);
+	user_irq_3_ev_pending_write(newword);
+}
+#define CSR_USER_IRQ_3_EV_ENABLE_ADDR (CSR_BASE + 0x8014L)
+#define CSR_USER_IRQ_3_EV_ENABLE_SIZE 1
+static inline uint32_t user_irq_3_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8014L);
+}
+static inline void user_irq_3_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8014L);
+}
+#define CSR_USER_IRQ_3_EV_ENABLE_I0_OFFSET 0
+#define CSR_USER_IRQ_3_EV_ENABLE_I0_SIZE 1
+static inline uint32_t user_irq_3_ev_enable_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_3_ev_enable_i0_read(void) {
+	uint32_t word = user_irq_3_ev_enable_read();
+	return user_irq_3_ev_enable_i0_extract(word);
+}
+static inline uint32_t user_irq_3_ev_enable_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_3_ev_enable_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_3_ev_enable_read();
+	uint32_t newword = user_irq_3_ev_enable_i0_replace(oldword, plain_value);
+	user_irq_3_ev_enable_write(newword);
+}
+
+/* user_irq_4 */
+#define CSR_USER_IRQ_4_BASE (CSR_BASE + 0x8800L)
+#define CSR_USER_IRQ_4_IN_ADDR (CSR_BASE + 0x8800L)
+#define CSR_USER_IRQ_4_IN_SIZE 1
+static inline uint32_t user_irq_4_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8800L);
+}
+#define CSR_USER_IRQ_4_MODE_ADDR (CSR_BASE + 0x8804L)
+#define CSR_USER_IRQ_4_MODE_SIZE 1
+static inline uint32_t user_irq_4_mode_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8804L);
+}
+static inline void user_irq_4_mode_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8804L);
+}
+#define CSR_USER_IRQ_4_EDGE_ADDR (CSR_BASE + 0x8808L)
+#define CSR_USER_IRQ_4_EDGE_SIZE 1
+static inline uint32_t user_irq_4_edge_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8808L);
+}
+static inline void user_irq_4_edge_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8808L);
+}
+#define CSR_USER_IRQ_4_EV_STATUS_ADDR (CSR_BASE + 0x880cL)
+#define CSR_USER_IRQ_4_EV_STATUS_SIZE 1
+static inline uint32_t user_irq_4_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x880cL);
+}
+#define CSR_USER_IRQ_4_EV_STATUS_I0_OFFSET 0
+#define CSR_USER_IRQ_4_EV_STATUS_I0_SIZE 1
+static inline uint32_t user_irq_4_ev_status_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_4_ev_status_i0_read(void) {
+	uint32_t word = user_irq_4_ev_status_read();
+	return user_irq_4_ev_status_i0_extract(word);
+}
+#define CSR_USER_IRQ_4_EV_PENDING_ADDR (CSR_BASE + 0x8810L)
+#define CSR_USER_IRQ_4_EV_PENDING_SIZE 1
+static inline uint32_t user_irq_4_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8810L);
+}
+static inline void user_irq_4_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8810L);
+}
+#define CSR_USER_IRQ_4_EV_PENDING_I0_OFFSET 0
+#define CSR_USER_IRQ_4_EV_PENDING_I0_SIZE 1
+static inline uint32_t user_irq_4_ev_pending_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_4_ev_pending_i0_read(void) {
+	uint32_t word = user_irq_4_ev_pending_read();
+	return user_irq_4_ev_pending_i0_extract(word);
+}
+static inline uint32_t user_irq_4_ev_pending_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_4_ev_pending_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_4_ev_pending_read();
+	uint32_t newword = user_irq_4_ev_pending_i0_replace(oldword, plain_value);
+	user_irq_4_ev_pending_write(newword);
+}
+#define CSR_USER_IRQ_4_EV_ENABLE_ADDR (CSR_BASE + 0x8814L)
+#define CSR_USER_IRQ_4_EV_ENABLE_SIZE 1
+static inline uint32_t user_irq_4_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x8814L);
+}
+static inline void user_irq_4_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x8814L);
+}
+#define CSR_USER_IRQ_4_EV_ENABLE_I0_OFFSET 0
+#define CSR_USER_IRQ_4_EV_ENABLE_I0_SIZE 1
+static inline uint32_t user_irq_4_ev_enable_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_4_ev_enable_i0_read(void) {
+	uint32_t word = user_irq_4_ev_enable_read();
+	return user_irq_4_ev_enable_i0_extract(word);
+}
+static inline uint32_t user_irq_4_ev_enable_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_4_ev_enable_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_4_ev_enable_read();
+	uint32_t newword = user_irq_4_ev_enable_i0_replace(oldword, plain_value);
+	user_irq_4_ev_enable_write(newword);
+}
+
+/* user_irq_5 */
+#define CSR_USER_IRQ_5_BASE (CSR_BASE + 0x9000L)
+#define CSR_USER_IRQ_5_IN_ADDR (CSR_BASE + 0x9000L)
+#define CSR_USER_IRQ_5_IN_SIZE 1
+static inline uint32_t user_irq_5_in_read(void) {
+	return csr_read_simple(CSR_BASE + 0x9000L);
+}
+#define CSR_USER_IRQ_5_MODE_ADDR (CSR_BASE + 0x9004L)
+#define CSR_USER_IRQ_5_MODE_SIZE 1
+static inline uint32_t user_irq_5_mode_read(void) {
+	return csr_read_simple(CSR_BASE + 0x9004L);
+}
+static inline void user_irq_5_mode_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x9004L);
+}
+#define CSR_USER_IRQ_5_EDGE_ADDR (CSR_BASE + 0x9008L)
+#define CSR_USER_IRQ_5_EDGE_SIZE 1
+static inline uint32_t user_irq_5_edge_read(void) {
+	return csr_read_simple(CSR_BASE + 0x9008L);
+}
+static inline void user_irq_5_edge_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x9008L);
+}
+#define CSR_USER_IRQ_5_EV_STATUS_ADDR (CSR_BASE + 0x900cL)
+#define CSR_USER_IRQ_5_EV_STATUS_SIZE 1
+static inline uint32_t user_irq_5_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x900cL);
+}
+#define CSR_USER_IRQ_5_EV_STATUS_I0_OFFSET 0
+#define CSR_USER_IRQ_5_EV_STATUS_I0_SIZE 1
+static inline uint32_t user_irq_5_ev_status_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_5_ev_status_i0_read(void) {
+	uint32_t word = user_irq_5_ev_status_read();
+	return user_irq_5_ev_status_i0_extract(word);
+}
+#define CSR_USER_IRQ_5_EV_PENDING_ADDR (CSR_BASE + 0x9010L)
+#define CSR_USER_IRQ_5_EV_PENDING_SIZE 1
+static inline uint32_t user_irq_5_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x9010L);
+}
+static inline void user_irq_5_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x9010L);
+}
+#define CSR_USER_IRQ_5_EV_PENDING_I0_OFFSET 0
+#define CSR_USER_IRQ_5_EV_PENDING_I0_SIZE 1
+static inline uint32_t user_irq_5_ev_pending_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_5_ev_pending_i0_read(void) {
+	uint32_t word = user_irq_5_ev_pending_read();
+	return user_irq_5_ev_pending_i0_extract(word);
+}
+static inline uint32_t user_irq_5_ev_pending_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_5_ev_pending_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_5_ev_pending_read();
+	uint32_t newword = user_irq_5_ev_pending_i0_replace(oldword, plain_value);
+	user_irq_5_ev_pending_write(newword);
+}
+#define CSR_USER_IRQ_5_EV_ENABLE_ADDR (CSR_BASE + 0x9014L)
+#define CSR_USER_IRQ_5_EV_ENABLE_SIZE 1
+static inline uint32_t user_irq_5_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x9014L);
+}
+static inline void user_irq_5_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x9014L);
+}
+#define CSR_USER_IRQ_5_EV_ENABLE_I0_OFFSET 0
+#define CSR_USER_IRQ_5_EV_ENABLE_I0_SIZE 1
+static inline uint32_t user_irq_5_ev_enable_i0_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t user_irq_5_ev_enable_i0_read(void) {
+	uint32_t word = user_irq_5_ev_enable_read();
+	return user_irq_5_ev_enable_i0_extract(word);
+}
+static inline uint32_t user_irq_5_ev_enable_i0_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void user_irq_5_ev_enable_i0_write(uint32_t plain_value) {
+	uint32_t oldword = user_irq_5_ev_enable_read();
+	uint32_t newword = user_irq_5_ev_enable_i0_replace(oldword, plain_value);
+	user_irq_5_ev_enable_write(newword);
+}
+
+/* user_irq_ena */
+#define CSR_USER_IRQ_ENA_BASE (CSR_BASE + 0x9800L)
+#define CSR_USER_IRQ_ENA_OUT_ADDR (CSR_BASE + 0x9800L)
+#define CSR_USER_IRQ_ENA_OUT_SIZE 1
+static inline uint32_t user_irq_ena_out_read(void) {
+	return csr_read_simple(CSR_BASE + 0x9800L);
+}
+static inline void user_irq_ena_out_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x9800L);
+}
+
+#endif
diff --git a/caravel_firmware/include/csr_defs.h b/caravel_firmware/include/csr_defs.h
new file mode 100644
index 000000000..d98e8dfb7
--- /dev/null
+++ b/caravel_firmware/include/csr_defs.h
@@ -0,0 +1,11 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */
diff --git a/caravel_firmware/include/defs.h b/caravel_firmware/include/defs.h
new file mode 100755
index 000000000..7181f0aec
--- /dev/null
+++ b/caravel_firmware/include/defs.h
@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _DEF_H_
+#define _DEF_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "csr.h"
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0  (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1  (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0  (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+//#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*) CSR_UART_RXTX_ADDR)
+#define reg_uart_txfull   (*(volatile uint32_t*) CSR_UART_TXFULL_ADDR)
+#define reg_uart_enable (*(volatile uint32_t*) CSR_UART_ENABLED_OUT_ADDR)
+
+// DEBUG (0x2000_0000)
+//#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_reset   (*(volatile uint32_t*) CSR_CTRL_RESET_ADDR)
+#define reg_debug_data   (*(volatile uint32_t*) CSR_DEBUG_RXTX_ADDR)
+#define reg_debug_txfull   (*(volatile uint32_t*) CSR_DEBUG_TXFULL_ADDR)
+#define reg_debug_irq_en   (*(volatile uint32_t*) CSR_USER_IRQ_3_EV_ENABLE_ADDR)
+//#define reg_debug_enable (*(volatile uint32_t*) CSR_UART_ENABLED_OUT_ADDR)
+
+// System Area (0x2F00_0000)
+#define reg_power_good    (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest  (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source    (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// --------------------------------------------------------
+#endif
diff --git a/caravel_firmware/include/gpio_controls.h b/caravel_firmware/include/gpio_controls.h
new file mode 100644
index 000000000..c27ec36c1
--- /dev/null
+++ b/caravel_firmware/include/gpio_controls.h
@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _GPIO_CONTROLS_H_
+#define _GPIO_CONTROLS_H_
+
+#include <stdint.h>
+
+// GPIO (0x2100_0000)
+#define reg_gpio_mode1  (*(volatile uint32_t*) CSR_GPIO_MODE1_ADDR)
+#define reg_gpio_mode0  (*(volatile uint32_t*) CSR_GPIO_MODE0_ADDR)
+#define reg_gpio_ien    (*(volatile uint32_t*) CSR_GPIO_IEN_ADDR)
+#define reg_gpio_oe     (*(volatile uint32_t*) CSR_GPIO_OE_ADDR)
+#define reg_gpio_in     (*(volatile uint32_t*) CSR_GPIO_IN_ADDR)
+#define reg_gpio_out    (*(volatile uint32_t*) CSR_GPIO_OUT_ADDR)
+//#define reg_gpio_pu   (*(volatile uint32_t*)0x21000008)
+//#define reg_gpio_pd   (*(volatile uint32_t*)0x2100000c)
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE	  0x0001
+#define OUTPUT_DISABLE	  0x0002
+#define HOLD_OVERRIDE	  0x0004
+#define INPUT_DISABLE	  0x0008
+#define MODE_SELECT	  0x0010
+#define ANALOG_ENABLE	  0x0020
+#define ANALOG_SELECT	  0x0040
+#define ANALOG_POLARITY	  0x0080
+#define SLOW_SLEW_MODE	  0x0100
+#define TRIPPOINT_SEL	  0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL    0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP	   0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT	   0x1809
+#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   0x1801
+#define GPIO_MODE_MGMT_STD_ANALOG   	   0x000b
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL	   0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN  0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP	   0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT	   0x1808
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL   0x1800
+#define GPIO_MODE_USER_STD_OUT_MONITORED   0x1802
+#define GPIO_MODE_USER_STD_ANALOG   	   0x000a
+
+#endif
diff --git a/caravel_firmware/include/irq.h b/caravel_firmware/include/irq.h
new file mode 100644
index 000000000..96328f807
--- /dev/null
+++ b/caravel_firmware/include/irq.h
@@ -0,0 +1,44 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "system.h"
+#include "csr_defs.h"
+
+static inline unsigned int irq_getie(void)
+{
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	unsigned int mask;
+	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+	return mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+}
+
+static inline unsigned int irq_pending(void)
+{
+	unsigned int pending;
+	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+	return pending;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/caravel_firmware/include/logic_analyser_controls.h b/caravel_firmware/include/logic_analyser_controls.h
new file mode 100644
index 000000000..134014ca0
--- /dev/null
+++ b/caravel_firmware/include/logic_analyser_controls.h
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _LOGIC_ANALYSER_CONTROLS_H_
+#define _LOGIC_ANALYSER_CONTROLS_H_
+
+#include <stdint.h>
+#include "csr.h"
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la3_data (*(volatile uint32_t*) CSR_LA_OUT_ADDR)
+#define reg_la2_data (*(volatile uint32_t*) (CSR_LA_OUT_ADDR + 4))
+#define reg_la1_data (*(volatile uint32_t*) (CSR_LA_OUT_ADDR + 8))
+#define reg_la0_data (*(volatile uint32_t*) (CSR_LA_OUT_ADDR + 12))
+
+#define reg_la3_data_in (*(volatile uint32_t*) CSR_LA_IN_ADDR)
+#define reg_la2_data_in (*(volatile uint32_t*) (CSR_LA_IN_ADDR + 4))
+#define reg_la1_data_in (*(volatile uint32_t*) (CSR_LA_IN_ADDR + 8))
+#define reg_la0_data_in (*(volatile uint32_t*) (CSR_LA_IN_ADDR + 12))
+
+#define reg_la3_oenb (*(volatile uint32_t*) CSR_LA_OE_ADDR)
+#define reg_la2_oenb (*(volatile uint32_t*) (CSR_LA_OE_ADDR + 4))
+#define reg_la1_oenb (*(volatile uint32_t*) (CSR_LA_OE_ADDR + 8))
+#define reg_la0_oenb (*(volatile uint32_t*) (CSR_LA_OE_ADDR + 12))
+
+#define reg_la3_iena (*(volatile uint32_t*) CSR_LA_IEN_ADDR)
+#define reg_la2_iena (*(volatile uint32_t*) (CSR_LA_IEN_ADDR + 4))
+#define reg_la1_iena (*(volatile uint32_t*) (CSR_LA_IEN_ADDR + 8))
+#define reg_la0_iena (*(volatile uint32_t*) (CSR_LA_IEN_ADDR + 12))
+
+#define reg_la_sample (*(volatile uint32_t*)0x25000030)
+
+#endif
diff --git a/caravel_firmware/include/register_definitions.h b/caravel_firmware/include/register_definitions.h
new file mode 100644
index 000000000..146b6a2f8
--- /dev/null
+++ b/caravel_firmware/include/register_definitions.h
@@ -0,0 +1,98 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _DEF_H_
+#define _DEF_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <csr.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0  (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1  (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0  (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+//#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*) CSR_UART_RXTX_ADDR)
+#define reg_uart_txfull   (*(volatile uint32_t*) CSR_UART_TXFULL_ADDR)
+#define reg_uart_enable (*(volatile uint32_t*) CSR_UART_ENABLED_OUT_ADDR)
+
+// DEBUG (0x2000_0000)
+//#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_reset   (*(volatile uint32_t*) CSR_CTRL_RESET_ADDR)
+#define reg_debug_data   (*(volatile uint32_t*) CSR_DEBUG_RXTX_ADDR)
+#define reg_debug_txfull   (*(volatile uint32_t*) CSR_DEBUG_TXFULL_ADDR)
+#define reg_debug_irq_en   (*(volatile uint32_t*) CSR_USER_IRQ_3_EV_ENABLE_ADDR)
+//#define reg_debug_enable (*(volatile uint32_t*) CSR_UART_ENABLED_OUT_ADDR)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la3_data (*(volatile uint32_t*) CSR_LA_OUT_ADDR)
+#define reg_la2_data (*(volatile uint32_t*) (CSR_LA_OUT_ADDR + 4))
+#define reg_la1_data (*(volatile uint32_t*) (CSR_LA_OUT_ADDR + 8))
+#define reg_la0_data (*(volatile uint32_t*) (CSR_LA_OUT_ADDR + 12))
+
+#define reg_la3_data_in (*(volatile uint32_t*) CSR_LA_IN_ADDR)
+#define reg_la2_data_in (*(volatile uint32_t*) (CSR_LA_IN_ADDR + 4))
+#define reg_la1_data_in (*(volatile uint32_t*) (CSR_LA_IN_ADDR + 8))
+#define reg_la0_data_in (*(volatile uint32_t*) (CSR_LA_IN_ADDR + 12))
+
+#define reg_la3_oenb (*(volatile uint32_t*) CSR_LA_OE_ADDR)
+#define reg_la2_oenb (*(volatile uint32_t*) (CSR_LA_OE_ADDR + 4))
+#define reg_la1_oenb (*(volatile uint32_t*) (CSR_LA_OE_ADDR + 8))
+#define reg_la0_oenb (*(volatile uint32_t*) (CSR_LA_OE_ADDR + 12))
+
+#define reg_la3_iena (*(volatile uint32_t*) CSR_LA_IEN_ADDR)
+#define reg_la2_iena (*(volatile uint32_t*) (CSR_LA_IEN_ADDR + 4))
+#define reg_la1_iena (*(volatile uint32_t*) (CSR_LA_IEN_ADDR + 8))
+#define reg_la0_iena (*(volatile uint32_t*) (CSR_LA_IEN_ADDR + 12))
+
+#define reg_la_sample (*(volatile uint32_t*)0x25000030)
+
+
+// System Area (0x2F00_0000)
+#define reg_power_good    (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest  (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source    (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// --------------------------------------------------------
+#endif
diff --git a/caravel_firmware/include/soc.h b/caravel_firmware/include/soc.h
new file mode 100644
index 000000000..e3909c425
--- /dev/null
+++ b/caravel_firmware/include/soc.h
@@ -0,0 +1,98 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (9a0be7a) & LiteX (017dfc8) on 2021-12-07 10:21:22
+//--------------------------------------------------------------------------------
+#ifndef __GENERATED_SOC_H
+#define __GENERATED_SOC_H
+#define CONFIG_CLOCK_FREQUENCY 10000000
+#define CONFIG_CPU_HAS_INTERRUPT
+#define CONFIG_CPU_RESET_ADDR 268435456
+#define CONFIG_CPU_TYPE_VEXRISCV
+#define CONFIG_CPU_VARIANT_MINIMAL
+#define CONFIG_CPU_HUMAN_NAME "VexRiscv_MinDebug"
+#define CONFIG_CPU_NOP "nop"
+#define SPIFLASH_PHY_FREQUENCY 10000000
+#define SPIFLASH_MODULE_NAME "W25Q128JV"
+#define SPIFLASH_MODULE_TOTAL_SIZE 16777216
+#define SPIFLASH_MODULE_PAGE_SIZE 256
+#define SPIFLASH_MODULE_QUAD_CAPABLE
+#define CONFIG_CSR_DATA_WIDTH 32
+#define CONFIG_CSR_ALIGNMENT 32
+#define CONFIG_BUS_STANDARD "WISHBONE"
+#define CONFIG_BUS_DATA_WIDTH 32
+#define CONFIG_BUS_ADDRESS_WIDTH 32
+#define TIMER0_INTERRUPT 0
+#define UART_INTERRUPT 1
+#define USER_IRQ_0_INTERRUPT 2
+#define USER_IRQ_1_INTERRUPT 3
+#define USER_IRQ_2_INTERRUPT 4
+#define USER_IRQ_3_INTERRUPT 5
+#define USER_IRQ_4_INTERRUPT 6
+#define USER_IRQ_5_INTERRUPT 7
+
+#ifndef __ASSEMBLER__
+static inline int config_clock_frequency_read(void) {
+	return 10000000;
+}
+static inline int config_cpu_reset_addr_read(void) {
+	return 268435456;
+}
+static inline const char * config_cpu_human_name_read(void) {
+	return "VexRiscv_MinDebug";
+}
+static inline const char * config_cpu_nop_read(void) {
+	return "nop";
+}
+static inline int spiflash_phy_frequency_read(void) {
+	return 10000000;
+}
+static inline const char * spiflash_module_name_read(void) {
+	return "W25Q128JV";
+}
+static inline int spiflash_module_total_size_read(void) {
+	return 16777216;
+}
+static inline int spiflash_module_page_size_read(void) {
+	return 256;
+}
+static inline int config_csr_data_width_read(void) {
+	return 32;
+}
+static inline int config_csr_alignment_read(void) {
+	return 32;
+}
+static inline const char * config_bus_standard_read(void) {
+	return "WISHBONE";
+}
+static inline int config_bus_data_width_read(void) {
+	return 32;
+}
+static inline int config_bus_address_width_read(void) {
+	return 32;
+}
+static inline int timer0_interrupt_read(void) {
+	return 0;
+}
+static inline int uart_interrupt_read(void) {
+	return 1;
+}
+static inline int user_irq_0_interrupt_read(void) {
+	return 2;
+}
+static inline int user_irq_1_interrupt_read(void) {
+	return 3;
+}
+static inline int user_irq_2_interrupt_read(void) {
+	return 4;
+}
+static inline int user_irq_3_interrupt_read(void) {
+	return 5;
+}
+static inline int user_irq_4_interrupt_read(void) {
+	return 6;
+}
+static inline int user_irq_5_interrupt_read(void) {
+	return 7;
+}
+#endif // !__ASSEMBLER__
+
+#endif
diff --git a/caravel_firmware/include/spi_controls.h b/caravel_firmware/include/spi_controls.h
new file mode 100644
index 000000000..6cb8032a6
--- /dev/null
+++ b/caravel_firmware/include/spi_controls.h
@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SPI_CONTROLS_H_
+#define _SPI_CONTROLS_H_
+
+#include <stdint.h>
+#include "csr.h"
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0	0x00000001
+#define FLASH_BITBANG_IO1	0x00000002
+#define FLASH_BITBANG_CLK	0x00000010
+#define FLASH_BITBANG_CSB	0x00000020
+#define FLASH_BITBANG_OEB0	0x00000100
+#define FLASH_BITBANG_OEB1	0x00000200
+#define FLASH_ENABLE		0x80000000
+
+// SPI Master Configuration
+//#define reg_spimaster_config (*(volatile uint32_t*) 0x24000000)
+#define reg_spimaster_control (*(volatile uint32_t*) CSR_SPI_MASTER_CONTROL_ADDR)
+#define reg_spimaster_status (*(volatile uint32_t*) CSR_SPI_MASTER_STATUS_ADDR)
+//#define reg_spimaster_data   (*(volatile uint32_t*) 0x24000004)
+#define reg_spimaster_wdata   (*(volatile uint32_t*) CSR_SPI_MASTER_MOSI_ADDR)
+#define reg_spimaster_rdata   (*(volatile uint32_t*) CSR_SPI_MASTER_MISO_ADDR)
+#define reg_spimaster_cs   (*(volatile uint32_t*) CSR_SPI_MASTER_CS_ADDR)
+#define reg_spimaster_clk_divider   (*(volatile uint32_t*) CSR_SPI_MASTER_CLK_DIVIDER_ADDR)
+#define reg_spi_enable (*(volatile uint32_t*) CSR_SPI_ENABLED_OUT_ADDR)
+
+// Bit fields for SPI master configuration
+//#define SPI_MASTER_DIV_MASK	0x00ff
+//#define SPI_MASTER_MLB		0x0100
+//#define SPI_MASTER_INV_CSB	0x0200
+//#define SPI_MASTER_INV_CLK	0x0400
+//#define SPI_MASTER_MODE_1	0x0800
+//#define SPI_MASTER_STREAM	0x1000
+//#define SPI_MASTER_ENABLE	0x2000
+//#define SPI_MASTER_IRQ_ENABLE	0x4000
+//#define SPI_HOUSEKEEPING_CONN	0x8000
+
+#endif
diff --git a/caravel_firmware/include/system.h b/caravel_firmware/include/system.h
new file mode 100644
index 000000000..fa1fe90e6
--- /dev/null
+++ b/caravel_firmware/include/system.h
@@ -0,0 +1,75 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#include "csr_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef CONFIG_CPU_TYPE_VEXRISCV
+
+__attribute__((unused)) static void flush_cpu_icache(void)
+{
+#if defined(CONFIG_CPU_HAS_ICACHE)
+  asm volatile(
+    ".word(0x100F)\n"
+    "nop\n"
+    "nop\n"
+    "nop\n"
+    "nop\n"
+    "nop\n"
+  );
+#endif
+}
+
+__attribute__((unused)) static void flush_cpu_dcache(void)
+{
+#if defined(CONFIG_CPU_HAS_DCACHE)
+  asm volatile(".word(0x500F)\n");
+#endif
+}
+
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+void busy_wait_us(unsigned int us);
+
+#define csrr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csrw(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define csrs(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
+
+#define csrc(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
+
+#else
+
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+void busy_wait_us(unsigned int us);
+
+#endif /* CONFIG_CPU_TYPE_VEXRISCV */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/caravel_firmware/include/timer_controls.h b/caravel_firmware/include/timer_controls.h
new file mode 100644
index 000000000..9e236d093
--- /dev/null
+++ b/caravel_firmware/include/timer_controls.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _TIMER_CONTROLS_H_
+#define _TIMER_CONTROLS_H_
+
+#include <stdint.h>
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*) CSR_TIMER0_EN_ADDR)
+#define reg_timer0_update  (*(volatile uint32_t*) CSR_TIMER0_UPDATE_VALUE_ADDR)
+#define reg_timer0_value  (*(volatile uint32_t*) CSR_TIMER0_VALUE_ADDR)
+#define reg_timer0_data   (*(volatile uint32_t*) CSR_TIMER0_LOAD_ADDR)
+#define reg_timer0_irq_en   (*(volatile uint32_t*) CSR_TIMER0_EV_ENABLE_ADDR)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value  (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data   (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE		0x01
+#define TIMER_ONESHOT		0x02
+#define TIMER_UPCOUNT		0x04
+#define TIMER_CHAIN		0x08
+#define TIMER_IRQ_ENABLE	0x10
+
+#endif
diff --git a/caravel_firmware/include/uart_controls.h b/caravel_firmware/include/uart_controls.h
new file mode 100644
index 000000000..678230345
--- /dev/null
+++ b/caravel_firmware/include/uart_controls.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _UART_CONTROLS_H_
+#define _UART_CONTROLS_H_
+
+#include <stdint.h>
+#include "csr.h"
+
+// UART (0x2000_0000)
+//#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*) CSR_UART_RXTX_ADDR)
+#define reg_uart_txfull   (*(volatile uint32_t*) CSR_UART_TXFULL_ADDR)
+#define reg_uart_enable (*(volatile uint32_t*) CSR_UART_ENABLED_OUT_ADDR)
+
+void writeSingleCharacterToUart(const char);
+void writeToUart(const char*);
+
+#endif
diff --git a/caravel_firmware/include/user_project_controls.h b/caravel_firmware/include/user_project_controls.h
new file mode 100644
index 000000000..38d12cca0
--- /dev/null
+++ b/caravel_firmware/include/user_project_controls.h
@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _USER_PROJECT_CONTROLS_H_
+#define _USER_PROJECT_CONTROLS_H_
+
+#include <stdint.h>
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+#define reg_wb_enable	  (*(volatile uint32_t*)0xf0003800)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr  (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_irq  (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datal (*(volatile uint32_t*)0x2600000c)
+#define reg_mprj_datah (*(volatile uint32_t*)0x26000010)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000038)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x2600003c)
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000048)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x2600004c)
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000058)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x2600005c)
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000068)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x2600006c)
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000078)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x2600007c)
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000088)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x2600008c)
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x2600009c)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x260000a0)
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b4)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b8)
+
+
+#endif
diff --git a/caravel_firmware/linker_scripts/sections.lds b/caravel_firmware/linker_scripts/sections.lds
new file mode 100644
index 000000000..10a820c26
--- /dev/null
+++ b/caravel_firmware/linker_scripts/sections.lds
@@ -0,0 +1,77 @@
+/* INCLUDE ../../generated/output_format.ld */
+
+OUTPUT_FORMAT("elf32-littleriscv")
+
+ENTRY(_start)
+
+__DYNAMIC = 0;
+
+/* INCLUDE ../../generated/regions.ld */
+
+MEMORY {
+	vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100
+	dff : ORIGIN = 0x00000000, LENGTH = 0x00000400
+	sram : ORIGIN = 0x01000000, LENGTH = 0x00000800
+	flash : ORIGIN = 0x10000000, LENGTH = 0x01000000
+	mprj : ORIGIN = 0x30000000, LENGTH = 0x00100000
+	hk : ORIGIN = 0x26000000, LENGTH = 0x00100000
+	csr : ORIGIN = 0xf0000000, LENGTH = 0x00010000
+}
+
+SECTIONS
+{
+	.text :
+	{
+		_ftext = .;
+		/* Make sure crt0 files come first, and they, and the isr */
+		/* don't get disposed of by greedy optimisation */
+		*crt0*(.text)
+		KEEP(*crt0*(.text))
+		KEEP(*(.text.isr))
+
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		_etext = .;
+	} > flash
+
+	.rodata :
+	{
+		. = ALIGN(8);
+		_frodata = .;
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		*(.rodata1)
+		. = ALIGN(8);
+		_erodata = .;
+	} > flash
+
+	.data :
+	{
+		. = ALIGN(8);
+		_fdata = .;
+		*(.data .data.* .gnu.linkonce.d.*)
+		*(.data1)
+		_gp = ALIGN(16);
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+		. = ALIGN(8);
+		_edata = .;
+	} > dff AT > flash
+
+	.bss :
+	{
+		. = ALIGN(8);
+		_fbss = .;
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(8);
+		_ebss = .;
+		_end = .;
+	} > dff
+}
+
+PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram));
+
+PROVIDE(_fdata_rom = LOADADDR(.data));
+PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
diff --git a/caravel_firmware/src/CMakeLists.txt b/caravel_firmware/src/CMakeLists.txt
new file mode 100644
index 000000000..26f09262e
--- /dev/null
+++ b/caravel_firmware/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_subdirectory(crt)
+add_subdirectory(isr)
+add_subdirectory(uart_controls)
+add_subdirectory(testcases)
diff --git a/caravel_firmware/src/crt/CMakeLists.txt b/caravel_firmware/src/crt/CMakeLists.txt
new file mode 100644
index 000000000..676d74407
--- /dev/null
+++ b/caravel_firmware/src/crt/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_library(CRT0 STATIC crt0_vex.s)
+
+target_link_libraries(CRT0 PRIVATE ISR)
diff --git a/caravel_firmware/src/crt/crt0_vex.s b/caravel_firmware/src/crt/crt0_vex.s
new file mode 100644
index 000000000..6ac5b42ae
--- /dev/null
+++ b/caravel_firmware/src/crt/crt0_vex.s
@@ -0,0 +1,91 @@
+.global main
+.global isr
+.global _start
+
+_start:
+  j crt_init
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+
+.global  trap_entry
+trap_entry:
+  sw x1,  - 1*4(sp)
+  sw x5,  - 2*4(sp)
+  sw x6,  - 3*4(sp)
+  sw x7,  - 4*4(sp)
+  sw x10, - 5*4(sp)
+  sw x11, - 6*4(sp)
+  sw x12, - 7*4(sp)
+  sw x13, - 8*4(sp)
+  sw x14, - 9*4(sp)
+  sw x15, -10*4(sp)
+  sw x16, -11*4(sp)
+  sw x17, -12*4(sp)
+  sw x28, -13*4(sp)
+  sw x29, -14*4(sp)
+  sw x30, -15*4(sp)
+  sw x31, -16*4(sp)
+  addi sp,sp,-16*4
+  call isr
+  lw x1 , 15*4(sp)
+  lw x5,  14*4(sp)
+  lw x6,  13*4(sp)
+  lw x7,  12*4(sp)
+  lw x10, 11*4(sp)
+  lw x11, 10*4(sp)
+  lw x12,  9*4(sp)
+  lw x13,  8*4(sp)
+  lw x14,  7*4(sp)
+  lw x15,  6*4(sp)
+  lw x16,  5*4(sp)
+  lw x17,  4*4(sp)
+  lw x28,  3*4(sp)
+  lw x29,  2*4(sp)
+  lw x30,  1*4(sp)
+  lw x31,  0*4(sp)
+  addi sp,sp,16*4
+  mret
+  .text
+
+
+crt_init:
+  la sp, _fstack
+  la a0, trap_entry
+  csrw mtvec, a0
+
+data_init:
+  la a0, _fdata
+  la a1, _edata
+  la a2, _fdata_rom
+data_loop:
+  beq a0,a1,data_done
+  lw a3,0(a2)
+  sw a3,0(a0)
+  add a0,a0,4
+  add a2,a2,4
+  j data_loop
+data_done:
+
+bss_init:
+  la a0, _fbss
+  la a1, _ebss
+bss_loop:
+  beq a0,a1,bss_done
+  sw zero,0(a0)
+  add a0,a0,4
+#ifndef SIM
+  j bss_loop
+#endif
+bss_done:
+  /* 880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt) */
+  li a0, 0x880
+  csrw mie,a0
+
+  call main
+infinit_loop:
+  j infinit_loop
diff --git a/caravel_firmware/src/isr/CMakeLists.txt b/caravel_firmware/src/isr/CMakeLists.txt
new file mode 100644
index 000000000..114f8e939
--- /dev/null
+++ b/caravel_firmware/src/isr/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_library(ISR STATIC isr.c)
+
+target_include_directories(ISR PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
diff --git a/caravel_firmware/src/isr/isr.c b/caravel_firmware/src/isr/isr.c
new file mode 100644
index 000000000..97d7826ce
--- /dev/null
+++ b/caravel_firmware/src/isr/isr.c
@@ -0,0 +1,51 @@
+// This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+// License: BSD
+
+#include "logic_analyser_controls.h"
+#include "irq.h"
+
+void isr(void);
+
+#ifdef CONFIG_CPU_HAS_INTERRUPT
+
+uint16_t flag;
+
+void isr(void)
+{
+//	__attribute__((unused)) unsigned int irqs;
+//
+//	irqs = irq_pending() & irq_getmask();
+//
+	irq_setmask(0);
+//
+//    reg_timer0_irq_en = 0; // disable interrupt
+//    reg_debug_irq_en = 0;
+
+//    reg_reset = 1;
+//    asm volatile ("slli x0, x0, 0x1f");
+//    asm volatile ("ebreak");
+//    asm volatile ("srai x0, x0, 7");
+
+   reg_la1_data = 0xa;
+   reg_la0_data = 0x20000;
+   flag = 1;
+
+//	if(irqs & (1 << TIMER0_INTERRUPT)) {
+////		uart_isr();
+//        reg_la1_data = 0xa;	// Signal end of test 1st stage
+//        reg_la0_data = 0x20000;
+//        flag = 1;
+//    }
+    return;
+
+//#ifndef UART_POLLING
+//	if(irqs & (1 << UART_INTERRUPT))
+//		uart_isr();
+//#endif
+}
+
+#else
+
+void isr(void){};
+
+#endif
diff --git a/caravel_firmware/src/testcases/CMakeLists.txt b/caravel_firmware/src/testcases/CMakeLists.txt
new file mode 100644
index 000000000..957d24d2e
--- /dev/null
+++ b/caravel_firmware/src/testcases/CMakeLists.txt
@@ -0,0 +1,13 @@
+add_subdirectory(io_ports)
+add_subdirectory(la_test1)
+add_subdirectory(la_test2)
+add_subdirectory(wb_port)
+add_subdirectory(mprj_stimulus)
+
+# foreach(TESTCASE )
+#     add_custom_command(
+#         TARGET ${TESTCASE}
+#         POST_BUILD
+#         COMMAND ${CMAKE_OBJCOPY} -O verilog $<TARGET_FILE:${TESTCASE}>
+#                 ${CMAKE_CURRENT_BINARY_DIR}/$<TARGET_NAME:${TESTCASE}>.hex
+#     )
diff --git a/caravel_firmware/src/testcases/io_ports/CMakeLists.txt b/caravel_firmware/src/testcases/io_ports/CMakeLists.txt
new file mode 100644
index 000000000..cfb3752d9
--- /dev/null
+++ b/caravel_firmware/src/testcases/io_ports/CMakeLists.txt
@@ -0,0 +1,18 @@
+set(TESTCASE io_ports)
+
+add_executable(${TESTCASE}
+    main.c)
+
+target_include_directories(${TESTCASE} PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
+
+target_link_libraries(${TESTCASE} PRIVATE CRT0)
+
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${CMAKE_SOURCE_DIR}/linker_scripts/sections.lds")
+
+add_custom_command(
+    TARGET ${TESTCASE}
+    POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O verilog $<TARGET_FILE:${TESTCASE}>
+            ${CMAKE_CURRENT_BINARY_DIR}/$<TARGET_NAME:${TESTCASE}>.hex
+)
diff --git a/verilog/dv/io_ports/io_ports.c b/caravel_firmware/src/testcases/io_ports/main.c
similarity index 96%
rename from verilog/dv/io_ports/io_ports.c
rename to caravel_firmware/src/testcases/io_ports/main.c
index d204e4a11..daa10651c 100644
--- a/verilog/dv/io_ports/io_ports.c
+++ b/caravel_firmware/src/testcases/io_ports/main.c
@@ -16,8 +16,9 @@
  */
 
 // This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
+#include "gpio_controls.h"
+#include "user_project_controls.h"
+// #include <stub.c>
 
 /*
 	IO Test:
@@ -27,7 +28,7 @@
 
 void main()
 {
-	/* 
+	/*
 	IO Control Registers
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
@@ -35,8 +36,8 @@ void main()
 	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
+
+
 	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
@@ -72,4 +73,3 @@ void main()
 	reg_mprj_xfer = 1;
 	while (reg_mprj_xfer == 1);
 }
-
diff --git a/caravel_firmware/src/testcases/la_test1/CMakeLists.txt b/caravel_firmware/src/testcases/la_test1/CMakeLists.txt
new file mode 100644
index 000000000..b29a4e5dd
--- /dev/null
+++ b/caravel_firmware/src/testcases/la_test1/CMakeLists.txt
@@ -0,0 +1,18 @@
+set(TESTCASE la_test1)
+
+add_executable(${TESTCASE}
+    main.c)
+
+target_include_directories(${TESTCASE} PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
+
+target_link_libraries(${TESTCASE} PRIVATE CRT0 UartControls)
+
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${CMAKE_SOURCE_DIR}/linker_scripts/sections.lds")
+
+add_custom_command(
+    TARGET ${TESTCASE}
+    POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O verilog $<TARGET_FILE:${TESTCASE}>
+            ${CMAKE_CURRENT_BINARY_DIR}/$<TARGET_NAME:${TESTCASE}>.hex
+)
diff --git a/verilog/dv/la_test1/la_test1.c b/caravel_firmware/src/testcases/la_test1/main.c
similarity index 93%
rename from verilog/dv/la_test1/la_test1.c
rename to caravel_firmware/src/testcases/la_test1/main.c
index cad69d115..83f8aaada 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/caravel_firmware/src/testcases/la_test1/main.c
@@ -15,15 +15,16 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
+#include "user_project_controls.h"
+#include "gpio_controls.h"
+#include "uart_controls.h"
+#include "logic_analyser_controls.h"
 
 // --------------------------------------------------------
 
 /*
 	MPRJ Logic Analyzer Test:
-		- Observes counter value through LA probes [31:0] 
+		- Observes counter value through LA probes [31:0]
 		- Sets counter initial value through LA probes [63:32]
 		- Flags when counter value exceeds 500 through the management SoC gpio
 		- Outputs message to the UART when the test concludes successfuly
@@ -50,7 +51,7 @@ void main()
 
 	// The upper GPIO pins are configured to be output
 	// and accessble to the management SoC.
-	// Used to flad the start/end of a test 
+	// Used to flad the start/end of a test
 	// The lower GPIO pins are configured to be output
 	// and accessible to the user project.  They show
 	// the project count value, although this test is
@@ -101,21 +102,21 @@ void main()
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-    // Configure LA probes [31:0], [127:64] as inputs to the cpu 
+    // Configure LA probes [31:0], [127:64] as inputs to the cpu
 	// Configure LA probes [63:32] as outputs from the cpu
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
 	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
 	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
 
-	// Flag start of the test 
+	// Flag start of the test
 	reg_mprj_datal = 0xAB400000;
 
 	// Set Counter value to zero through LA probes [63:32]
 	reg_la1_data = 0x00000000;
 
 	// Configure LA probes from [63:32] as inputs to disable counter write
-	reg_la1_oenb = reg_la1_iena = 0x00000000;    
+	reg_la1_oenb = reg_la1_iena = 0x00000000;
 
 	while (1) {
 		if (reg_la0_data_in > 0x1F4) {
@@ -127,4 +128,3 @@ void main()
 	print("Monitor: Test 1 Passed\n\n");	// Makes simulation very long!
 	reg_mprj_datal = 0xAB510000;
 }
-
diff --git a/caravel_firmware/src/testcases/la_test2/CMakeLists.txt b/caravel_firmware/src/testcases/la_test2/CMakeLists.txt
new file mode 100644
index 000000000..b2aabe66d
--- /dev/null
+++ b/caravel_firmware/src/testcases/la_test2/CMakeLists.txt
@@ -0,0 +1,18 @@
+set(TESTCASE la_test2)
+
+add_executable(${TESTCASE}
+    main.c)
+
+target_include_directories(${TESTCASE} PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
+
+target_link_libraries(${TESTCASE} PRIVATE CRT0)
+
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${CMAKE_SOURCE_DIR}/linker_scripts/sections.lds")
+
+add_custom_command(
+    TARGET ${TESTCASE}
+    POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O verilog $<TARGET_FILE:${TESTCASE}>
+            ${CMAKE_CURRENT_BINARY_DIR}/$<TARGET_NAME:${TESTCASE}>.hex
+)
diff --git a/verilog/dv/la_test2/la_test2.c b/caravel_firmware/src/testcases/la_test2/main.c
similarity index 92%
rename from verilog/dv/la_test2/la_test2.c
rename to caravel_firmware/src/testcases/la_test2/main.c
index 25fad481e..39e9dadb4 100644
--- a/verilog/dv/la_test2/la_test2.c
+++ b/caravel_firmware/src/testcases/la_test2/main.c
@@ -15,14 +15,15 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
+#include "user_project_controls.h"
+#include "gpio_controls.h"
+#include "spi_controls.h"
+#include "logic_analyser_controls.h"
 
 /*
 	MPRJ LA Test:
 		- Sets counter clk through LA[64]
-		- Sets counter rst through LA[65] 
+		- Sets counter rst through LA[65]
 		- Observes count value for five clk cycle through LA[31:0]
 */
 
@@ -44,7 +45,7 @@ void main()
 
 
 	// All GPIO pins are configured to be output
-	// Used to flad the start/end of a test 
+	// Used to flad the start/end of a test
 
         reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
         reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -83,7 +84,7 @@ void main()
         reg_mprj_xfer = 1;
         while (reg_mprj_xfer == 1);
 
-	// Configure All LA probes as inputs to the cpu 
+	// Configure All LA probes as inputs to the cpu
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
 	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
@@ -93,7 +94,7 @@ void main()
 	reg_mprj_datal = 0xAB600000;
 
 	// Configure LA[64] LA[65] as outputs from the cpu
-	reg_la2_oenb = reg_la2_iena = 0x00000003; 
+	reg_la2_oenb = reg_la2_iena = 0x00000003;
 
 	// Set clk & reset to one
 	reg_la2_data = 0x00000003;
@@ -114,7 +115,7 @@ void main()
                         reg_mprj_datal = 0xAB610000;
                         break;
                 }
-                
+
         }
 
 }
diff --git a/caravel_firmware/src/testcases/mprj_stimulus/CMakeLists.txt b/caravel_firmware/src/testcases/mprj_stimulus/CMakeLists.txt
new file mode 100644
index 000000000..6a649632a
--- /dev/null
+++ b/caravel_firmware/src/testcases/mprj_stimulus/CMakeLists.txt
@@ -0,0 +1,18 @@
+set(TESTCASE mprj_stimulus)
+
+add_executable(${TESTCASE}
+    main.c)
+
+target_include_directories(${TESTCASE} PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
+
+target_link_libraries(${TESTCASE} PRIVATE CRT0)
+
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${CMAKE_SOURCE_DIR}/linker_scripts/sections.lds")
+
+add_custom_command(
+    TARGET ${TESTCASE}
+    POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O verilog $<TARGET_FILE:${TESTCASE}>
+            ${CMAKE_CURRENT_BINARY_DIR}/$<TARGET_NAME:${TESTCASE}>.hex
+)
diff --git a/caravel_firmware/src/testcases/mprj_stimulus/main.c b/caravel_firmware/src/testcases/mprj_stimulus/main.c
new file mode 100644
index 000000000..c58cc70b7
--- /dev/null
+++ b/caravel_firmware/src/testcases/mprj_stimulus/main.c
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "user_project_controls.h"
+#include "gpio_controls.h"
+#include "spi_controls.h"
+#include "logic_analyser_controls.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+    // The upper GPIO pins are configured to be output
+    // and accessble to the management SoC.
+    // Used to flag the start/end of a test
+    // The lower GPIO pins are configured to be output
+    // and accessible to the user project.  They show
+    // the project count value, although this test is
+    // designed to read the project count through the
+    // logic analyzer probes.
+    // I/O 6 is configured for the UART Tx line
+
+    uint32_t testval;
+
+    reg_spi_enable = 0;
+
+    // reg_spimaster_cs = 0x00000000;		// Shut off the housekeeping SPI,
+					// so we can use the pins.
+
+    reg_mprj_datal = 0x00000000;
+    reg_mprj_datah = 0x00000000;
+
+    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_6  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUT_MONITORED;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    /* TEST:  Recast channels 35 to 32 to allow input to user project	*/
+    /* This is done locally only:  Do not run reg_mprj_xfer!		*/
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Configure LA probes [31:0], [127:64] as inputs to the cpu
+    // Configure LA probes [63:32] as outputs from the cpu
+    reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+    reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+    reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+    reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
+
+    // Flag start of the test
+    reg_mprj_datal = 0xAB400000;
+
+    // Set Counter value to zero through LA probes [63:32]
+    reg_la1_data = 0x00000000;
+
+    // Configure LA probes from [63:32] as inputs to disable counter write
+    reg_la1_oenb = reg_la1_iena = 0x00000000;
+
+    reg_mprj_datal = 0xAB410000;
+    reg_mprj_datah = 0x00000000;
+
+    // Test ability to force data on channel 37
+    // NOTE:  Only the low 6 bits of reg_mprj_datah are meaningful
+
+    reg_mprj_datah = 0x0f0f0fc0;
+    reg_mprj_datah = 0x00000000;
+    reg_mprj_datah = 0x0f0f0fca;
+    reg_mprj_datah = 0x0000000a;
+    reg_mprj_datah = 0x0f0f0fc0;
+    reg_mprj_datah = 0x00000000;
+    reg_mprj_datah = 0x0f0f0fc5;
+    reg_mprj_datah = 0x00000005;
+
+    // Test ability to read back data generated by the user project
+    // on the "monitored" outputs.  Read from the lower 16 bits and
+    // copy the value to the upper 16 bits.
+
+    testval = reg_mprj_datal;
+    reg_mprj_datal = (testval << 16);
+    testval = reg_mprj_datal;
+    reg_mprj_datal = (testval << 16);
+
+    // Flag end of the test
+    reg_mprj_datal = 0xAB510000;
+}
diff --git a/caravel_firmware/src/testcases/wb_port/CMakeLists.txt b/caravel_firmware/src/testcases/wb_port/CMakeLists.txt
new file mode 100644
index 000000000..3591824f4
--- /dev/null
+++ b/caravel_firmware/src/testcases/wb_port/CMakeLists.txt
@@ -0,0 +1,18 @@
+set(TESTCASE wb_port)
+
+add_executable(${TESTCASE}
+    main.c)
+
+target_include_directories(${TESTCASE} PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
+
+target_link_libraries(${TESTCASE} PRIVATE CRT0)
+
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${CMAKE_SOURCE_DIR}/linker_scripts/sections.lds")
+
+add_custom_command(
+    TARGET ${TESTCASE}
+    POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O verilog $<TARGET_FILE:${TESTCASE}>
+            ${CMAKE_CURRENT_BINARY_DIR}/$<TARGET_NAME:${TESTCASE}>.hex
+)
diff --git a/verilog/dv/wb_port/wb_port.c b/caravel_firmware/src/testcases/wb_port/main.c
similarity index 96%
rename from verilog/dv/wb_port/wb_port.c
rename to caravel_firmware/src/testcases/wb_port/main.c
index 4f590556c..9b3551af9 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/caravel_firmware/src/testcases/wb_port/main.c
@@ -16,8 +16,10 @@
  */
 
 // This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
+#include "user_project_controls.h"
+#include "logic_analyser_controls.h"
+#include "gpio_controls.h"
+#include "spi_controls.h"
 
 /*
 	Wishbone Test:
@@ -28,15 +30,15 @@
 void main()
 {
 
-	/* 
+	/*
 	IO Control Registers
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
 	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
+
+
 	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
diff --git a/caravel_firmware/src/uart_controls/CMakeLists.txt b/caravel_firmware/src/uart_controls/CMakeLists.txt
new file mode 100644
index 000000000..4c352bd87
--- /dev/null
+++ b/caravel_firmware/src/uart_controls/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_library(UartControls STATIC uart_controls.c)
+
+target_include_directories(UartControls PRIVATE
+    ${CMAKE_SOURCE_DIR}/include)
diff --git a/caravel_firmware/src/uart_controls/uart_controls.c b/caravel_firmware/src/uart_controls/uart_controls.c
new file mode 100644
index 000000000..be6f52b34
--- /dev/null
+++ b/caravel_firmware/src/uart_controls/uart_controls.c
@@ -0,0 +1,16 @@
+#include "uart_controls.h"
+
+void writeSingleCharacterToUart(const char character) {
+	if (character == '\n') {
+		writeSingleCharacterToUart('\r');
+	}
+	while (reg_uart_txfull == 1) {};
+	reg_uart_data = character;
+}
+
+
+void writeToUart(const char* string) {
+	while (*string != '\0') {
+		writeSingleCharacterToUart(*(string++));
+	}
+}
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 43a414971..633dfbe75 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -25,11 +25,11 @@ PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
 all:  ${PATTERNS}
 
 	for i in ${PATTERNS}; do \
-		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+		( cd $$i && make sim -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
 	done
 
 DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
-$(DV_PATTERNS): verify-% : 
+$(DV_PATTERNS): verify-% :
 	cd $* && make
 
 clean:  ${PATTERNS}
@@ -37,5 +37,5 @@ clean:  ${PATTERNS}
 		( cd $$i && \rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe ) ; \
 	done
 	rm -rf *.log
-	
+
 .PHONY: clean all
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
index 3fd0b560d..c52cd9e28 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/io_ports/Makefile
@@ -15,18 +15,67 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
- 
+
 PWDD := $(shell pwd)
 BLOCKS := $(shell basename $(PWDD))
+CARAVEL_USER_PROJECT_ROOT=$(shell readlink -f ../../../)
 
 # ---- Include Partitioned Makefiles ----
 
 CONFIG = caravel_user_project
 
+# Simulation variables
+SIM?=RTL
+DESIGNS?=${CARAVEL_USER_PROJECT_ROOT}
+CARAVEL_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+CORE_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel_mgmt_soc_litex/verilog
+export CARAVEL_PATH=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+export VERILOG_PATH=${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG=${CARAVEL_USER_PROJECT_ROOT}/verilog
+
+# Firmware variables
+TESTCASE=io_ports
+PATH := /opt/riscv32i/bin:${PATH}
+FIRMWARE_SOURCE_DIR := ${CARAVEL_USER_PROJECT_ROOT}/caravel_firmware
+FIRMWARE_BUILD_DIR := ${CARAVEL_USER_PROJECT_ROOT}/build
+
+.PHONY: configure
+configure:
+	cmake \
+	-DCMAKE_TOOLCHAIN_FILE=${FIRMWARE_SOURCE_DIR}/cmake/vexriscv_toolchain.cmake \
+	-B${FIRMWARE_BUILD_DIR} \
+	${FIRMWARE_SOURCE_DIR}
+
+.PHONY: build
+build: configure
+	cmake --build ${FIRMWARE_BUILD_DIR}
+
+.PHONY: rebuild
+rebuild: configure
+	cmake --build ${FIRMWARE_BUILD_DIR} --clean-first
+
+.PHONY: sim
+sim: rebuild
+	cp -f ${FIRMWARE_BUILD_DIR}/src/testcases/${TESTCASE}/${TESTCASE}.hex .
+	sed -ie 's/@10/@00/g' ${TESTCASE}.hex
+	iverilog \
+	-Ttyp \
+	-DFUNCTIONAL \
+	-DSIM \
+	-DUSE_POWER_PINS \
+	-DUNIT_DELAY=#1 \
+	-f${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog/includes/includes.rtl.${CONFIG} \
+	-o ${TESTCASE}.vvp ${TESTCASE}_tb.v
+	vvp ${TESTCASE}.vvp
+	mv ${TESTCASE}.vcd RTL-${TESTCASE}.vcd
 
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+.PHONY: clean
+clean: clean-build clean-hex
 
+.PHONY: clean-build
+clean-build:
+	cmake --build ${FIRMWARE_BUILD_DIR} --target clean
 
+.PHONY: clean-hex
+clean-hex:
+	rm *.hex *.hexe
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
index 3fd0b560d..882a089e9 100644
--- a/verilog/dv/la_test1/Makefile
+++ b/verilog/dv/la_test1/Makefile
@@ -15,18 +15,67 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
- 
+
 PWDD := $(shell pwd)
 BLOCKS := $(shell basename $(PWDD))
+CARAVEL_USER_PROJECT_ROOT=$(shell readlink -f ../../../)
 
 # ---- Include Partitioned Makefiles ----
 
 CONFIG = caravel_user_project
 
+# Simulation variables
+SIM?=RTL
+DESIGNS?=${CARAVEL_USER_PROJECT_ROOT}
+CARAVEL_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+CORE_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel_mgmt_soc_litex/verilog
+export CARAVEL_PATH=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+export VERILOG_PATH=${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG=${CARAVEL_USER_PROJECT_ROOT}/verilog
+
+# Firmware variables
+TESTCASE=la_test1
+PATH := /opt/riscv32i/bin:${PATH}
+FIRMWARE_SOURCE_DIR=${CARAVEL_USER_PROJECT_ROOT}/caravel_firmware
+FIRMWARE_BUILD_DIR=${CARAVEL_USER_PROJECT_ROOT}/build
+
+.PHONY: configure
+configure:
+	cmake \
+	-DCMAKE_TOOLCHAIN_FILE=${FIRMWARE_SOURCE_DIR}/cmake/vexriscv_toolchain.cmake \
+	-B${FIRMWARE_BUILD_DIR} \
+	${FIRMWARE_SOURCE_DIR}
+
+.PHONY: build
+build: configure
+	cmake --build ${FIRMWARE_BUILD_DIR}
+
+.PHONY: rebuild
+rebuild: configure
+	cmake --build ${FIRMWARE_BUILD_DIR} --clean-first
+
+.PHONY: sim
+sim: build
+	cp ${FIRMWARE_BUILD_DIR}/src/testcases/${TESTCASE}/${TESTCASE}.hex .
+	sed -ie 's/@10/@00/g' ${TESTCASE}.hex
+	iverilog \
+	-Ttyp \
+	-DFUNCTIONAL \
+	-DSIM \
+	-DUSE_POWER_PINS \
+	-DUNIT_DELAY=#1 \
+	-f${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog/includes/includes.rtl.${CONFIG} \
+	-o ${TESTCASE}.vvp ${TESTCASE}_tb.v
+	vvp ${TESTCASE}.vvp
+	mv ${TESTCASE}.vcd RTL-${TESTCASE}.vcd
 
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+.PHONY: clean
+clean: clean-build clean-hex
 
+.PHONY: clean-build
+clean-build:
+	cmake --build ${FIRMWARE_BUILD_DIR} --target clean
 
+.PHONY: clean-hex
+clean-hex:
+	rm *.hex *.hexe
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
index 3fd0b560d..c1243d604 100644
--- a/verilog/dv/la_test2/Makefile
+++ b/verilog/dv/la_test2/Makefile
@@ -15,18 +15,67 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
- 
+
 PWDD := $(shell pwd)
 BLOCKS := $(shell basename $(PWDD))
+CARAVEL_USER_PROJECT_ROOT=$(shell readlink -f ../../../)
 
 # ---- Include Partitioned Makefiles ----
 
 CONFIG = caravel_user_project
 
+# Simulation variables
+SIM?=RTL
+DESIGNS?=${CARAVEL_USER_PROJECT_ROOT}
+CARAVEL_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+CORE_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel_mgmt_soc_litex/verilog
+export CARAVEL_PATH=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+export VERILOG_PATH=${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG=${CARAVEL_USER_PROJECT_ROOT}/verilog
+
+# Firmware variables
+TESTCASE=la_test2
+PATH := /opt/riscv32i/bin:${PATH}
+FIRMWARE_SOURCE_DIR=${CARAVEL_USER_PROJECT_ROOT}/caravel_firmware
+FIRMWARE_BUILD_DIR=${CARAVEL_USER_PROJECT_ROOT}/build
+
+.PHONY: configure
+configure:
+	cmake \
+	-DCMAKE_TOOLCHAIN_FILE=${FIRMWARE_SOURCE_DIR}/cmake/vexriscv_toolchain.cmake \
+	-B${FIRMWARE_BUILD_DIR} \
+	${FIRMWARE_SOURCE_DIR}
+
+.PHONY: build
+build: configure
+	cmake --build ${FIRMWARE_BUILD_DIR}
+
+.PHONY: rebuild
+rebuild: configure
+	cmake --build ${FIRMWARE_BUILD_DIR} --clean-first
+
+.PHONY: sim
+sim: build
+	cp ${FIRMWARE_BUILD_DIR}/src/testcases/${TESTCASE}/${TESTCASE}.hex .
+	sed -ie 's/@10/@00/g' ${TESTCASE}.hex
+	iverilog \
+	-Ttyp \
+	-DFUNCTIONAL \
+	-DSIM \
+	-DUSE_POWER_PINS \
+	-DUNIT_DELAY=#1 \
+	-f${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog/includes/includes.rtl.${CONFIG} \
+	-o ${TESTCASE}.vvp ${TESTCASE}_tb.v
+	vvp ${TESTCASE}.vvp
+	mv ${TESTCASE}.vcd RTL-${TESTCASE}.vcd
 
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+.PHONY: clean
+clean: clean-build clean-hex
 
+.PHONY: clean-build
+clean-build:
+	cmake --build ${FIRMWARE_BUILD_DIR} --target clean
 
+.PHONY: clean-hex
+clean-hex:
+	rm *.hex *.hexe
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index 3fd0b560d..eaa9366a2 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -15,18 +15,67 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
- 
+
 PWDD := $(shell pwd)
 BLOCKS := $(shell basename $(PWDD))
+CARAVEL_USER_PROJECT_ROOT=$(shell readlink -f ../../../)
 
 # ---- Include Partitioned Makefiles ----
 
 CONFIG = caravel_user_project
 
+# Simulation variables
+SIM?=RTL
+DESIGNS?=${CARAVEL_USER_PROJECT_ROOT}
+CARAVEL_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+CORE_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel_mgmt_soc_litex/verilog
+export CARAVEL_PATH=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+export VERILOG_PATH=${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG=${CARAVEL_USER_PROJECT_ROOT}/verilog
+
+# Firmware variables
+TESTCASE=mprj_stimulus
+PATH := /opt/riscv32i/bin:${PATH}
+FIRMWARE_SOURCE_DIR=${CARAVEL_USER_PROJECT_ROOT}/caravel_firmware
+FIRMWARE_BUILD_DIR=${CARAVEL_USER_PROJECT_ROOT}/build
+
+.PHONY: configure
+configure:
+	cmake \
+	-DCMAKE_TOOLCHAIN_FILE=${FIRMWARE_SOURCE_DIR}/cmake/vexriscv_toolchain.cmake \
+	-B${FIRMWARE_BUILD_DIR} \
+	${FIRMWARE_SOURCE_DIR}
+
+.PHONY: build
+build: configure
+	cmake --build ${FIRMWARE_BUILD_DIR}
+
+.PHONY: rebuild
+rebuild: configure
+	cmake --build ${FIRMWARE_BUILD_DIR} --clean-first
+
+.PHONY: sim
+sim: build
+	cp ${FIRMWARE_BUILD_DIR}/src/testcases/${TESTCASE}/${TESTCASE}.hex .
+	sed -ie 's/@10/@00/g' ${TESTCASE}.hex
+	iverilog \
+	-Ttyp \
+	-DFUNCTIONAL \
+	-DSIM \
+	-DUSE_POWER_PINS \
+	-DUNIT_DELAY=#1 \
+	-f${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog/includes/includes.rtl.${CONFIG} \
+	-o ${TESTCASE}.vvp ${TESTCASE}_tb.v
+	vvp ${TESTCASE}.vvp
+	mv ${TESTCASE}.vcd RTL-${TESTCASE}.vcd
 
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+.PHONY: clean
+clean: clean-build clean-hex
 
+.PHONY: clean-build
+clean-build:
+	cmake --build ${FIRMWARE_BUILD_DIR} --target clean
 
+.PHONY: clean-hex
+clean-hex:
+	rm *.hex *.hexe
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 3fd0b560d..bee85ab96 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -15,18 +15,67 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
- 
+
 PWDD := $(shell pwd)
 BLOCKS := $(shell basename $(PWDD))
+CARAVEL_USER_PROJECT_ROOT=$(shell readlink -f ../../../)
 
 # ---- Include Partitioned Makefiles ----
 
 CONFIG = caravel_user_project
 
+# Simulation variables
+SIM?=RTL
+DESIGNS?=${CARAVEL_USER_PROJECT_ROOT}
+CARAVEL_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+CORE_VERILOG_PATH?=${CARAVEL_USER_PROJECT_ROOT}/caravel_mgmt_soc_litex/verilog
+export CARAVEL_PATH=${CARAVEL_USER_PROJECT_ROOT}/caravel/verilog
+export VERILOG_PATH=${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG=${CARAVEL_USER_PROJECT_ROOT}/verilog
+
+# Firmware variables
+TESTCASE=wb_port
+PATH := /opt/riscv32i/bin:${PATH}
+FIRMWARE_SOURCE_DIR=${CARAVEL_USER_PROJECT_ROOT}/caravel_firmware
+FIRMWARE_BUILD_DIR=${CARAVEL_USER_PROJECT_ROOT}/build
+
+.PHONY: configure
+configure:
+	cmake \
+	-DCMAKE_TOOLCHAIN_FILE=${FIRMWARE_SOURCE_DIR}/cmake/vexriscv_toolchain.cmake \
+	-B${FIRMWARE_BUILD_DIR} \
+	${FIRMWARE_SOURCE_DIR}
+
+.PHONY: build
+build: configure
+	cmake --build ${FIRMWARE_BUILD_DIR}
+
+.PHONY: rebuild
+rebuild: configure
+	cmake --build ${FIRMWARE_BUILD_DIR} --clean-first
+
+.PHONY: sim
+sim: build
+	cp ${FIRMWARE_BUILD_DIR}/src/testcases/${TESTCASE}/${TESTCASE}.hex .
+	sed -ie 's/@10/@00/g' ${TESTCASE}.hex
+	iverilog \
+	-Ttyp \
+	-DFUNCTIONAL \
+	-DSIM \
+	-DUSE_POWER_PINS \
+	-DUNIT_DELAY=#1 \
+	-f${CARAVEL_USER_PROJECT_ROOT}/mgmt_core_wrapper/verilog/includes/includes.rtl.${CONFIG} \
+	-o ${TESTCASE}.vvp ${TESTCASE}_tb.v
+	vvp ${TESTCASE}.vvp
+	mv ${TESTCASE}.vcd RTL-${TESTCASE}.vcd
 
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+.PHONY: clean
+clean: clean-build clean-hex
 
+.PHONY: clean-build
+clean-build:
+	cmake --build ${FIRMWARE_BUILD_DIR} --target clean
 
+.PHONY: clean-hex
+clean-hex:
+	rm *.hex *.hexe