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+ reference configs for hardening strategies
~ user project wrapper config to use strategy 1 + ahb counter macro configs
1 parent 46dfdfa commit 913ae1c

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10 files changed

+398
-16
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10 files changed

+398
-16
lines changed

‎openlane/ahb_counter/base.sdc‎

Lines changed: 100 additions & 0 deletions
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1+
2+
#------------------------------------------#
3+
# Pre-defined Constraints
4+
#------------------------------------------#
5+
6+
# Clock network
7+
if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
8+
set clk_input $::env(CLOCK_PORT)
9+
create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
10+
puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
11+
} else {
12+
set clk_input __VIRTUAL_CLK__
13+
create_clock -name clk -period $::env(CLOCK_PERIOD)
14+
puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
15+
}
16+
if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
17+
set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
18+
}
19+
if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
20+
set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
21+
}
22+
23+
# Clock non-idealities
24+
set_propagated_clock [all_clocks]
25+
set_clock_uncertainty $::env(CLOCK_UNCERTAINTY_CONSTRAINT) [get_clocks {clk}]
26+
puts "\[INFO\]: Setting clock uncertainity to: $::env(CLOCK_UNCERTAINTY_CONSTRAINT)"
27+
set_clock_transition $::env(CLOCK_TRANSITION_CONSTRAINT) [get_clocks {clk}]
28+
puts "\[INFO\]: Setting clock transition to: $::env(CLOCK_TRANSITION_CONSTRAINT)"
29+
30+
# Maximum transition time for the design nets
31+
set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
32+
puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
33+
34+
# Maximum fanout
35+
set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
36+
puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
37+
38+
# Timing paths delays derate
39+
set_timing_derate -early [expr {1-$::env(TIME_DERATING_CONSTRAINT)/100}]
40+
set_timing_derate -late [expr {1+$::env(TIME_DERATING_CONSTRAINT)/100}]
41+
puts "\[INFO\]: Setting timing derate to: $::env(TIME_DERATING_CONSTRAINT) %"
42+
43+
#------------------------------------------#
44+
# Retrieved Constraints
45+
#------------------------------------------#
46+
47+
# Clock source latency
48+
set clk_max_latency 4.85
49+
set clk_min_latency 2.22
50+
set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
51+
set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
52+
puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
53+
54+
# Clock input Transition
55+
set clk_tran 1.37
56+
set_input_transition $clk_tran [get_ports $clk_input]
57+
puts "\[INFO\]: Setting clock transition: $clk_tran"
58+
59+
# Input delays
60+
set_input_delay -max 10.38 -clock [get_clocks {clk}] [get_ports {HTRANS[*]}]
61+
set_input_delay -max 10.97 -clock [get_clocks {clk}] [get_ports {HWRITE}]
62+
set_input_delay -max 11.76 -clock [get_clocks {clk}] [get_ports {HSIZE[*]}]
63+
set_input_delay -max 12.12 -clock [get_clocks {clk}] [get_ports {HADDR[*]}]
64+
set_input_delay -max 4.01 -clock [get_clocks {clk}] [get_ports {HRESETn}]
65+
set_input_delay -max 4.58 -clock [get_clocks {clk}] [get_ports {HREADY}]
66+
set_input_delay -max 6.11 -clock [get_clocks {clk}] [get_ports {HWDATA[*]}]
67+
set_input_delay -min 0.63 -clock [get_clocks {clk}] [get_ports {HWRITE}]
68+
set_input_delay -min 0.7 -clock [get_clocks {clk}] [get_ports {HADDR[*]}]
69+
set_input_delay -min 0.83 -clock [get_clocks {clk}] [get_ports {HSIZE[*]}]
70+
set_input_delay -min 0.87 -clock [get_clocks {clk}] [get_ports {HTRANS[*]}]
71+
set_input_delay -min 1.05 -clock [get_clocks {clk}] [get_ports {HWDATA[*]}]
72+
set_input_delay -min 1.18 -clock [get_clocks {clk}] [get_ports {HREADY}]
73+
set_input_delay -min 2.33 -clock [get_clocks {clk}] [get_ports {HRESETn}]
74+
75+
# Input Transition
76+
set_input_transition -max 0.12 [get_ports {HSIZE[*]}]
77+
set_input_transition -max 0.13 [get_ports {HREADY}]
78+
set_input_transition -max 0.26 [get_ports {HWRITE}]
79+
set_input_transition -max 0.32 [get_ports {HTRANS[*]}]
80+
set_input_transition -max 0.49 [get_ports {HWDATA[*]}]
81+
set_input_transition -max 0.62 [get_ports {HRESETn}]
82+
set_input_transition -max 0.67 [get_ports {HADDR[*]}]
83+
set_input_transition -min 0.04 [get_ports {HADDR[*]}]
84+
set_input_transition -min 0.04 [get_ports {HWDATA[*]}]
85+
set_input_transition -min 0.12 [get_ports {HSIZE[*]}]
86+
set_input_transition -min 0.26 [get_ports {HWRITE}]
87+
set_input_transition -min 0.27 [get_ports {HRESETn}]
88+
set_input_transition -min 0.28 [get_ports {HREADY}]
89+
set_input_transition -min 0.32 [get_ports {HTRANS[*]}]
90+
91+
# Output delays
92+
set_output_delay -max 7.54 -clock [get_clocks {clk}] [get_ports {HRDATA[*]}]
93+
set_output_delay -max 9.8 -clock [get_clocks {clk}] [get_ports {HREADYOUT}]
94+
set_output_delay -min 0.01 -clock [get_clocks {clk}] [get_ports {HRDATA[*]}]
95+
set_output_delay -min 0.83 -clock [get_clocks {clk}] [get_ports {HREADYOUT}]
96+
97+
# Output loads
98+
set avg_load 0.10
99+
set max_load 0.29
100+
set_load $max_load [all_outputs]

‎openlane/ahb_counter/config.yaml‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
DESIGN_NAME: ahb_counter
2+
FP_PDN_MULTILAYER: false
3+
CLOCK_PORT: HCLK
4+
CLOCK_PERIOD: 23
5+
VERILOG_FILES:
6+
- dir::../../verilog/rtl/ahb_counter.v
7+
PNR_SDC_FILE: dir::base.sdc
8+
SIGNOFF_SDC_FILE: dir::signoff.sdc
9+
DESIGN_REPAIR_MAX_WIRE_LENGTH: 800
10+
RUN_POST_GRT_DESIGN_REPAIR: true
11+
FP_SIZING: absolute
12+
DIE_AREA: [0, 0, 400, 200]
13+
CORE_AREA: [10, 10, 390, 190]
14+
PL_TARGET_DENSITY_PCT: 50
15+
RUN_POST_GRT_RESIZER_TIMING: true
16+
TIME_DERATING_CONSTRAINT: 8.0
17+
VDD_NETS:
18+
- vccd1
19+
GND_NETS:
20+
- vssd1
21+
FP_PIN_ORDER_CFG: dir::pin_order.cfg

‎openlane/ahb_counter/pin_order.cfg‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
#BUS_SORT
2+
3+
#NR
4+
$10
5+
gpio.*
6+
7+
#S
8+
$10
9+
H.*

‎openlane/ahb_counter/signoff.sdc‎

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,94 @@
1+
2+
#------------------------------------------#
3+
# Pre-defined Constraints
4+
#------------------------------------------#
5+
6+
# Clock network
7+
if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
8+
set clk_input $::env(CLOCK_PORT)
9+
create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
10+
puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
11+
} else {
12+
set clk_input __VIRTUAL_CLK__
13+
create_clock -name clk -period $::env(CLOCK_PERIOD)
14+
puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
15+
}
16+
if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
17+
set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
18+
}
19+
if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
20+
set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
21+
}
22+
23+
# Clock non-idealities
24+
set_propagated_clock [all_clocks]
25+
set_clock_uncertainty 0.1 [get_clocks {clk}]
26+
puts "\[INFO\]: Setting clock uncertainity to: 0.1"
27+
28+
# Maximum fanout
29+
set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
30+
puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
31+
32+
# Timing paths delays derate
33+
set_timing_derate -early [expr {1-5.0/100}]
34+
set_timing_derate -late [expr {1+5.0/100}]
35+
puts "\[INFO\]: Setting timing derate to: 5.0 %"
36+
37+
#------------------------------------------#
38+
# Retrieved Constraints
39+
#------------------------------------------#
40+
41+
# Clock source latency
42+
set clk_max_latency 4.85
43+
set clk_min_latency 2.22
44+
set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
45+
set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
46+
puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
47+
48+
# Clock input Transition
49+
set clk_tran 1.37
50+
set_input_transition $clk_tran [get_ports $clk_input]
51+
puts "\[INFO\]: Setting clock transition: $clk_tran"
52+
53+
# Input delays
54+
set_input_delay -max 10.57 -clock [get_clocks {clk}] [get_ports {HWRITE}]
55+
set_input_delay -max 11.36 -clock [get_clocks {clk}] [get_ports {HSIZE[*]}]
56+
set_input_delay -max 11.72 -clock [get_clocks {clk}] [get_ports {HADDR[*]}]
57+
set_input_delay -max 3.61 -clock [get_clocks {clk}] [get_ports {HRESETn}]
58+
set_input_delay -max 4.18 -clock [get_clocks {clk}] [get_ports {HREADY}]
59+
set_input_delay -max 5.71 -clock [get_clocks {clk}] [get_ports {HWDATA[*]}]
60+
set_input_delay -max 9.98 -clock [get_clocks {clk}] [get_ports {HTRANS[*]}]
61+
set_input_delay -min 1.03 -clock [get_clocks {clk}] [get_ports {HWRITE}]
62+
set_input_delay -min 1.10 -clock [get_clocks {clk}] [get_ports {HADDR[*]}]
63+
set_input_delay -min 1.23 -clock [get_clocks {clk}] [get_ports {HSIZE[*]}]
64+
set_input_delay -min 1.27 -clock [get_clocks {clk}] [get_ports {HTRANS[*]}]
65+
set_input_delay -min 1.45 -clock [get_clocks {clk}] [get_ports {HWDATA[*]}]
66+
set_input_delay -min 1.58 -clock [get_clocks {clk}] [get_ports {HREADY}]
67+
set_input_delay -min 2.73 -clock [get_clocks {clk}] [get_ports {HRESETn}]
68+
69+
# Input Transition
70+
set_input_transition -max 0.12 [get_ports {HSIZE[*]}]
71+
set_input_transition -max 0.13 [get_ports {HREADY}]
72+
set_input_transition -max 0.26 [get_ports {HWRITE}]
73+
set_input_transition -max 0.32 [get_ports {HTRANS[*]}]
74+
set_input_transition -max 0.49 [get_ports {HWDATA[*]}]
75+
set_input_transition -max 0.62 [get_ports {HRESETn}]
76+
set_input_transition -max 0.67 [get_ports {HADDR[*]}]
77+
set_input_transition -min 0.04 [get_ports {HADDR[*]}]
78+
set_input_transition -min 0.04 [get_ports {HWDATA[*]}]
79+
set_input_transition -min 0.12 [get_ports {HSIZE[*]}]
80+
set_input_transition -min 0.26 [get_ports {HWRITE}]
81+
set_input_transition -min 0.27 [get_ports {HRESETn}]
82+
set_input_transition -min 0.28 [get_ports {HREADY}]
83+
set_input_transition -min 0.32 [get_ports {HTRANS[*]}]
84+
85+
# Output delays
86+
set_output_delay -max 7.14 -clock [get_clocks {clk}] [get_ports {HRDATA[*]}]
87+
set_output_delay -max 9.40 -clock [get_clocks {clk}] [get_ports {HREADYOUT}]
88+
set_output_delay -min 0.41 -clock [get_clocks {clk}] [get_ports {HRDATA[*]}]
89+
set_output_delay -min 1.23 -clock [get_clocks {clk}] [get_ports {HREADYOUT}]
90+
91+
# Output loads
92+
set avg_load 0.10
93+
set max_load 0.29
94+
set_load $max_load [all_outputs]

‎openlane/user_project_wrapper/base.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ puts "\[INFO\]: Setting timing derate to: $::env(TIME_DERATING_CONSTRAINT) %"
5151
#------------------------------------------#
5252

5353
# Clock source latency
54-
set clk_max_latency 3
54+
set clk_max_latency 4.85
5555
set clk_min_latency 2.22
5656
set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
5757
set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]

‎openlane/user_project_wrapper/config.yaml‎

Lines changed: 31 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,40 @@
11
# Design files
22
VERILOG_FILES:
33
- dir::../../verilog/rtl/defines.v
4-
- dir::../../verilog/rtl/ahb_counter.v
54
- dir::../../verilog/rtl/user_project_wrapper.v
65
PNR_SDC_FILE: dir::base.sdc
76

8-
# Hardening strategy variables (this is for 2-Full-Wrapper Flattening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info
9-
SYNTH_ELABORATE_ONLY: false
10-
RUN_POST_GPL_DESIGN_REPAIR: true
11-
RUN_POST_CTS_RESIZER_TIMING: true
12-
FP_PDN_ENABLE_RAILS: true
13-
RUN_ANTENNA_REPAIR: true
14-
RUN_FILL_INSERTION: true
15-
RUN_TAP_ENDCAP_INSERTION: true
16-
RUN_CTS: true
7+
# Hardening strategy variables (this is for 1-Macro-First Hardening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info
8+
SYNTH_ELABORATE_ONLY: true
9+
RUN_POST_GPL_DESIGN_REPAIR: false
10+
RUN_POST_CTS_RESIZER_TIMING: false
11+
DESIGN_REPAIR_BUFFER_INPUT_PORTS: false
12+
FP_PDN_ENABLE_RAILS: false
13+
RUN_ANTENNA_REPAIR: false
14+
RUN_FILL_INSERTION: false
15+
RUN_TAP_ENDCAP_INSERTION: false
16+
RUN_CTS: false
1717
RUN_IRDROP_REPORT: false
18+
ERROR_ON_SYNTH_CHECKS: false
19+
20+
# Macros configurations
21+
MACROS:
22+
ahb_counter:
23+
gds: dir::../../gds/ahb_counter.gds
24+
lef: dir::../../lef/ahb_counter.lef
25+
instances:
26+
frigate_prj:
27+
location: [450, 100]
28+
orientation: "N"
29+
nl: dir::../../verilog/gl/ahb_counter.v
30+
spef:
31+
min_*: dir::../../spef/multicorner/ahb_counter.min.spef
32+
nom_*: dir::../../spef/multicorner/ahb_counter.nom.spef
33+
max_*: dir::../../spef/multicorner/ahb_counter.max.spef
34+
lib:
35+
"*": dir::../../lib/ahb_counter.lib
36+
PDN_MACRO_CONNECTIONS:
37+
- frigate_prj vccd1 vssd1 vccd1 vssd1
1838

1939
# PDN configurations
2040
FP_PDN_VOFFSET: 15
@@ -27,8 +47,5 @@ FP_PDN_VPITCH: 90
2747
FP_PDN_HPITCH: 90
2848
ERROR_ON_PDN_VIOLATIONS: false
2949

30-
# Magic variables
50+
# Magic variables
3151
MAGIC_DRC_USE_GDS: true
32-
33-
# Project-specific Configurations
34-
ERROR_ON_SYNTH_CHECKS: false

‎openlane/user_project_wrapper/ref_configs/config_1.yaml‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
# Design files
2+
VERILOG_FILES:
3+
- dir::../../verilog/rtl/defines.v
4+
- dir::../../verilog/rtl/user_project_wrapper.v
5+
PNR_SDC_FILE: dir::base.sdc
6+
7+
# Hardening strategy variables (this is for 1-Macro-First Hardening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info
8+
SYNTH_ELABORATE_ONLY: true
9+
RUN_POST_GPL_DESIGN_REPAIR: false
10+
RUN_POST_CTS_RESIZER_TIMING: false
11+
DESIGN_REPAIR_BUFFER_INPUT_PORTS: false
12+
FP_PDN_ENABLE_RAILS: false
13+
RUN_ANTENNA_REPAIR: false
14+
RUN_FILL_INSERTION: false
15+
RUN_TAP_ENDCAP_INSERTION: false
16+
RUN_CTS: false
17+
RUN_IRDROP_REPORT: false
18+
ERROR_ON_SYNTH_CHECKS: false
19+
20+
# Macros configurations
21+
MACROS:
22+
ahb_counter:
23+
gds: dir::../../gds/ahb_counter.gds
24+
lef: dir::../../lef/ahb_counter.lef
25+
instances:
26+
frigate_prj:
27+
location: [450, 450]
28+
orientation: "N"
29+
nl: dir::../../verilog/gl/ahb_counter.v
30+
spef:
31+
min_*: dir::../../spef/multicorner/ahb_counter.min.spef
32+
nom_*: dir::../../spef/multicorner/ahb_counter.nom.spef
33+
max_*: dir::../../spef/multicorner/ahb_counter.max.spef
34+
lib:
35+
"*": dir::../../lib/ahb_counter.lib
36+
PDN_MACRO_CONNECTIONS:
37+
- frigate_prj vccd1 vssd1 vccd1 vssd1
38+
39+
# PDN configurations
40+
FP_PDN_VOFFSET: 15
41+
FP_PDN_HOFFSET: 15
42+
FP_PDN_VWIDTH: 3.1
43+
FP_PDN_HWIDTH: 3.1
44+
FP_PDN_VSPACING: 15.5
45+
FP_PDN_HSPACING: 15.5
46+
FP_PDN_VPITCH: 90
47+
FP_PDN_HPITCH: 90
48+
ERROR_ON_PDN_VIOLATIONS: false
49+
50+
# Magic variables
51+
MAGIC_DRC_USE_GDS: true
52+

‎openlane/user_project_wrapper/ref_configs/config_2.yaml‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# Design files
2+
VERILOG_FILES:
3+
- dir::../../verilog/rtl/defines.v
4+
- dir::../../verilog/rtl/ahb_counter.v
5+
- dir::../../verilog/rtl/user_project_wrapper.v
6+
PNR_SDC_FILE: dir::base.sdc
7+
8+
# Hardening strategy variables (this is for 2-Full-Wrapper Flattening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info
9+
SYNTH_ELABORATE_ONLY: false
10+
RUN_POST_GPL_DESIGN_REPAIR: true
11+
RUN_POST_CTS_RESIZER_TIMING: true
12+
RUN_POST_GRT_RESIZER_TIMING: true
13+
FP_PDN_ENABLE_RAILS: true
14+
RUN_ANTENNA_REPAIR: true
15+
RUN_FILL_INSERTION: true
16+
RUN_TAP_ENDCAP_INSERTION: true
17+
RUN_CTS: true
18+
RUN_IRDROP_REPORT: false
19+
20+
# PDN configurations
21+
FP_PDN_VOFFSET: 15
22+
FP_PDN_HOFFSET: 15
23+
FP_PDN_VWIDTH: 3.1
24+
FP_PDN_HWIDTH: 3.1
25+
FP_PDN_VSPACING: 15.5
26+
FP_PDN_HSPACING: 15.5
27+
FP_PDN_VPITCH: 90
28+
FP_PDN_HPITCH: 90
29+
ERROR_ON_PDN_VIOLATIONS: false
30+
31+
# Magic variables
32+
MAGIC_DRC_USE_GDS: true
33+
34+
# Project-specific Configurations
35+
ERROR_ON_SYNTH_CHECKS: false
36+
PL_TARGET_DENSITY_PCT: 50
37+
TIME_DERATING_CONSTRAINT: 7.5

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