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Merge pull request #288 from d-m-bailey/2409
Changes for the LVS system for 2409
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checks/be_checks/README.md

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# Backend Checks
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In your `caravel_user_project` or `caravel_user_project_analog` directory,
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create an LVS configuration file based on [digital user project wrapper lvs configuration](https://github.com/efabless/caravel_user_project/blob/main/lvs/user_project_wrapper/lvs_config.json) or [analog user project configuration](https://github.com/efabless/caravel_user_project_analog/blob/main/lvs/user_analog_project_wrapper/lvs_config.json).
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In your `caravel_user_project`, `caravel_user_project_analog`, `openframe_user_project`, or `caravel_user_mini` directory,
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create an LVS configuration file based on [digital user project wrapper lvs configuration](https://github.com/efabless/caravel_user_project/blob/main/lvs/user_project_wrapper/lvs_config.json), [analog user project configuration](https://github.com/efabless/caravel_user_project_analog/blob/main/lvs/user_analog_project_wrapper/lvs_config.json), [openframe user project configuration](https://github.com/efabless/openframe_user_project/blob/main/lvs/openframe_project_wrapper/lvs_config.json), or [digital mini user project configuration](https://github.com/efabless/caravel_user_mini/blob/main/lvs/user_project_wrapper_mini4/lvs_config.json).
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`mpw_precheck` expects this file to be in `lvs/<cellname>/lvs_config.json`.
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`LVS_SPICE_FILES` : A list of spice files.
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`LVS_VERILOG_FILES` : A list of verilog files. **Note: files with child modules should be listed before parent modules.**
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`LVS_VERILOG_FILES` : A list of verilog files. **Note: files with child modules may need to be listed before parent modules.**
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Optional variable lists: `*` may be used as a wild card character.
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Using this variable can prevent unwanted flattening of empty cells.
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This has no effect of cells that are flattened because of a small number of layers.
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Internal connectivity is maintained (at least at the top level).
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Cells that actually contain devices or hierarchies may also be abstracted.
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If actual abstraction processing was done on a cell, a lef file will be created in the extraction diretory.
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Be warned that this may take up over an hour for cells with many 100K subcells.
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Also be aware that abstracting a cell will connect all ports by name
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even if they are not internally connected.
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`EXTRACT_CREATE_SUBCUT` : List of cells to surround with the substrate isolation layer.
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The substrate isolation layer is used during LVS to virtually devide the substrate into regions
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that may be connected to different nets (ex. `vssa1` and `vssd1`).
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Without this layer all substrate connections are shorted and LVS is not possible.
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The isolation layer must not overlap any deep nwell or other isolation layers at sub-hierarchies.
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Specifing the cell here results in an isolation area excluding deep nwell and pre-exisiting isolation layers.
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This is a temporary layer but the actual shape is stored in a gds file in the extraction directory.
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WARNING: This should only be used with ground nets. It allows psubstrate to be
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connected to any single net within the region, including power!
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### LVS Options
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`LVS_FLATTEN` : List of cells to flatten before comparing,
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- Rerunning with --noextract is faster because previous extraction result will be used.
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- Add cells to the `EXTRACT_FLATGLOB` to flatten before extraction.
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- Cells in `EXTRACT_ABSTRACT` will be extracted (top level?), but netlisted as black-boxes.
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- Add cells to the `EXTRACT_CREATE_SUBCUT` to isolate the psubstrate.
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Use this when you have blocks with different substrate connections.
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- `LVS_FLATTEN` is a list of cell names to be flattened during LVS.
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Flattening cells with unmatched ports may resolve proxy port errors.
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- netgen normally flattens unmatched cells which can lead to confusing results at higher levels.

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